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Cost Reduction Methodology for FPGA Families

Wed, 03/14/2007 - 12:18pm
Lattice Semiconductor introduces the FreedomChip™ cost reduction methodology for its Extreme Performance LatticeSC and LatticeSCM (LatticeSC/M) FPGA families. The price of selected high-volume LatticeSC/M FPGA designs can be reduced from 30% to 75% by converting to the pin compatible Lattice FreedomChip device with a fully integrated, seamless design methodology. The FreedomChip methodology is a new approach to the challenge of FPGA cost reduction that employs industry standard ASIC techniques to comprehensively test a LatticeSC/M die to a specific design. Through automatic insertion of scan logic and dedicated silicon test features, the user’s netlist is implemented in low-cost, custom-tested silicon

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