Lattice Semiconductor Corporation announces the LatticeECP2M™ FPGA family, offering high-speed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the LatticeECP2 low cost architecture, the LatticeECP2M family has been developed on advanced 90 nm CMOS technology utilizing 300 mm wafers. Previously, high-speed embedded SERDES serial I/O with speeds over 3Gb/s was available only on relatively expensive high-end FPGAs. Integrating this capability into a low-cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video and industrial equipment.

Lattice Semiconductor Corporation