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60 GHz BiCMOS PLL

Mon, 05/08/2006 - 7:45am
As the demand for wireless devices above 50 GHz increases, SiGeC BiCMOS-based technologies will step up to the plate to offer cutting-edge technologies and competitive costs. This article discusses an integrated PLL, tunable from 54.5 to 57.8 GHz and manufactured in a SiGe:C BiCMOS technology.

By Wolfgang Winkler, Johannes Borngräber, Bernd Heinemann and Frank Herzel


Glossary of Acronyms

BiCMOS— Bipolar CMOS
BMBF— Bundesministerium für Bildung und Forschung (German Federal Ministry of Education and Research)
CMOS— Complementary Metal-Oxide Semiconductor
FET— Field-Effect Transistor
HBT— Heterojunction Bipolar Transistor
IF— Intermediate Frequency
MIM— Metal-Insulator-Metal
PFD— Phase-Frequency Detector
PLL— Phase-Locked Loop
RMS— Root-Mean-Square
Si— Silicon
SiGe:C— Silicon Germanium: Carbon
VCO— Voltage-Controlled Oscillator
WIGWAM— Wireless Gigabit with Advanced Multimedia Support
WLAN— Wireless Local Area Network

The PLL is aimed at wireless transceivers in the unlicensed band from 57 GHz to 64 GHz.1 Existing 60 GHz transceivers are based on compound semiconductors.2 By contrast, silicon-based solutions will enable a high integration level at low cost.



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Figure 1. Circuit schematic of the PLL.

The known 60 GHz systems use free-running oscillators for frequency synthesis. These solutions are subject to frequency changes because of device parameter variations with process and temperature. Our PLL solution allows a simple stabilization of the frequency. In June 2002, a 45 GHz PLL manufactured in a SiGe bipolar technology was described.3 It uses a VCO running at half the output frequency in conjunction with a frequency doubler.



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Photo 1. Chip photo of the fully integrated PLL.

In contrast, this PLL avoids a frequency doubler and uses a fundamental LC oscillator resulting in a higher output power at given power consumption. Furthermore, it is based on BiCMOS technology, which allows the combination of fast bipolar circuitry and low-power CMOS blocks to achieve a high integration level.


The schematic of the fully integrated PLL is shown in Figure 1. A VCO with both coarse- and fine-tuning inputs is embedded in a PLL with two parallel loops sharing the frequency divider and the PFD. This topology allows the combining of a relatively wide tuning range with a low-noise sensitivity.4 The coarse-tuning loop, with a tuning range of 3 GHz, has no resistor in the loop filter; only a large MIM capacitor to minimize the noise contribution. The fine-tuning loop contains a standard loop filter for stability. The fine-tuning range is as low as 600 MHz, which minimizes the noise contribution from the fine-tuning loop.



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Figure 2. VCO output frequency as a function of coarse-tuning voltage.

The PLL was fabricated in a SiGe:C BiCMOS technology with fT/fmax = 200 GHz/200 GHz.5


The PLL is shown in Photo 1. The chip size is 1000 × 800 µm2, including pads, and 700 × 560 µm2 without pads. The VCO is based on a modified Colpitts principle in a symmetric configuration similar to that shown in a paper by Winkler, et al., and is followed by a cascade of ten static dividers.6

With the symmetric signal, the sensitivity to substrate noise is reduced and the signal coupling to the symmetric ECL divider circuit, described in another paper by Winkler, et al., is more effective.7 Figure 2 shows the measured coarse-tuning range, which amounts to 3 GHz. Another 600 MHz tuning range results from the fine-tuning. A VCO frequency around 55 GHz will result in an IF of about 5 GHz in a 60 GHz heterodyne receiver. This will allow circuitry developed for 802.11a WLAN to be reused in an integrated 60 GHz WLAN transceiver. The measured PLL lock range is from 54.5 to 57.8 GHz.



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Figure 4. High-resolution output spectrum around the carrier including 20 dB external attenuations.


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Figure 3. Output spectrum of PLL including 20 dB external attenuation.

Figures 3 and 4 show the PLL output spectrum with different resolutions. The measurements were performed on wafer using the spectrum analyzer FSEM 30, in conjunction with the harmonic diode mixer FS-Z75, for frequency extension to the V-band. To prevent mixer overload, a 20 dB waveguide attenuator was inserted. The reference spurs are 50 dB below the carrier. The circuit operates from a 3 V supply except for the first divide-by-two stage, which needs a 4.3 V supply. A signal generator provides a sine-wave reference signal from 53.2 to 56.5 MHz with 100 mV amplitude. The total power consumption amounts to 650 mW.



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Figure 5. RMS phase error due to VCO noise vs. loop bandwidth fL.
An important issue is the optimization of the loop bandwidth. The high PLL-output frequency results in a large PLL-division factor if a commercial crystal oscillator is used to drive the PLL. This enhances the jitter contributions of the input signal and the charge pump, which are lowpass-filtered in a PLL making a narrowband PLL desirable. However, because of the absence of high-quality passives in an integrated PLL, the VCO phase noise, which is highpass-filtered in the PLL, will significantly degrade the PLL jitter performance. A paper by Herzel, et al.,8 shows that the corresponding RMS-phase-error contribution (in radians) can be deduced from the single-sideband phase noise SSSB [1/Hz] of the free-running VCO measured at the offset Δf from the carrier, and the loop bandwidth fL [Hz] according to:

Figure 5 shows the RMS phase error as a function of fL for two typical VCO-phase-noise values. A relatively large loop bandwidth will be required for an acceptable phase error, resulting in a subtle trade-off with the other noise contributions in the PLL. We conclude that the PLL bandwidth of 200 kHz visible in Figure 5 should be significantly increased in a redesign.



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Acknowledgment

The authors acknowledge the IHP technology team for chip fabrication. This work was partly funded by the German Federal Ministry of Education and Research (BMBF) under the project acronym WIGWAM.


References

1. W. Winkler et al., "60 GHz Transceiver Circuits in SiGe:C BiCMOS Technology," Proceedings of the ESSCIRC 2004, Leuven, Belgium, pp. 83-86, September 2004. 2. Y. Shoji, K. Hamaguchi, H. Ogawa. "Millimeter-Wave Remote Self-Heterodyne System for Extremely Stable and Low-Cost Broad-Band Signal Transmission," IEEE Transactions on Microwave Theory and Techniques, vol. 50, pp. 1458-1467, June 2002. 3. G. Ritzberger, J. Böck, A. Scholtz. "45 GHz Highly Integrated Phase-Locked Loop Frequency Synthesizer in SiGe Bipolar Technology," 2002 IEEE MTT-S International Microwave Symposium Digest, Seattle, USA, pp. 831-834, June 2002. 4. F. Herzel, G. Fischer, H. Gustat. "An Integrated CMOS RF Synthesizer for 802.11a Wireless LAN," IEEE J. Solid-State Circuits, vol. 38, pp. 1767-1770, October 2003. 5. B. Heinemann, et al. "Novel Collector Design for High-speed SiGe:C HBTs," Proceedings of the IEDM'02, San Francisco, pp. 775-778, December 2002. 6. W. Winkler, et al. "60 GHz and 76 GHz Oscillators in 0.25 µm SiGe:C BiCMOS," ISSCC Dig. Tech. Papers , San Francisco, pp. 454-455, February 2003. 7. W. Winkler, et al. "High Performance and Low-voltage Divider Circuits Fabricated in SiGe:C HBT Technology," ESSCIRC Digest of Technical Papers, pp. 827-830, September 2002. 8. F. Herzel, W. Winkler, J. Borngräber. "An Integrated 10 GHz Quadrature LC-VCO in SiGe:C BiCMOS Technology for Low-jitter Applications," Proceedings IEEE Custom Integrated Circuits Conf. (CICC), San Jose, CA, pp. 293-296, September 2003.


About the Authors

Wolfgang Winkler is a design engineer in the IHP in Frankfurt (Oder). His main research interests are circuits for wireless communication and radar in silicon-based technologies. For the past few years, he was involved in the design of building blocks for wireless transceivers at 60 GHz and radar circuits at 24 GHz and 77 GHz. Additionally, he designed benchmarking circuits for technology characterization and model verification. Wolfgang Winkler received an MS at the Technical University Ilmenau, Germany, in 1979, and a PhD in 1984, both in electrical engineering. Johannes Borngräber received his MS in Berlin in 1981, in mathematics. Between 1983 and 2003, he was involved in electron-beam lithography and test-field design with the IHP in Frankfurt (Oder), Germany. Since then, he has been working in the measurement of silicon ICs for RF and high-speed digital applications. Bernd Heinemann received an MS in physics from Humboldt University zu Berlin, Germany, in 1984, and a Dr.-Ing. degree in electrical engineering from Technische Universität Berlin, Germany, in 1997. In 1984, he joined the IHP, Frankfurt (Oder), were he worked on the modeling and fabrication of Si-based devices. His research interests include FET and bipolar transistors. Frank Herzel received his MS in Berlin in 1989, and a PhD in Rostock in 1993, both in theoretical physics. Since 1993, he has been with the IHP in Frankfurt (Oder), Germany, where he was mainly involved in semiconductor device and process modeling until 1996. Since 1996, he has been working in the design of silicon ICs for RF and high-speed digital applications.

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