As the annual increase in clock speed delivered by the semiconductor industry begins to slow, designers of high performance military systems are looking around for the next major innovation in electronics.
Glossary of AcronymsADC— Analog to Digital Converter
CDMA— Code-Division Multiple Access
CMOS— Complementary Metal-Oxide Semiconductor
DARPA— Defense Advanced Research Projects Agency
DSP— Digital Signal Processor
JTRS— Joint Tactical Radio System
MUOS— Mobile User Objective System
PA— Power Amplifier
PLL— Phase-Locked Loop
RAM— Random Access Memory
SFQ— Single Flux Quantum
SINAD— Signal to total noise and interference ratio
SME— Superconducting Microelectronics
VLSI— Very Large-Scale Integration
Superconductivity is considered by many to be the next level of performance enhancements for electronic components. While CMOS still holds the top position for components in terms of acceptable performance, cost and economies of scale, and CMOS engineers will continue to cram more transistors onto a piece of silicon for some time to come, physics is finally placing a limit on the speed that complex circuits can run at. They just get too hot.
Engineers and designers are well aware of the edge of the CMOS envelope. With that in mind, superconducting micro-electronics is moving closer and closer to the center of the radar screen. A series of complementary developments in cooler technology, fabrication processing and the design of the SME devices themselves have resulted in complex integrated circuits that deliver outstanding performance. ADC chips that sample a 20 GHz bandwidth, signal processing chips that clock at 40 GHz all produced by adapting fabrication equipment the semiconductor industry moved on from in the mid '80s. Simply by updating the processing technology SME is expected to deliver clock speeds of 200 GHz in the future. This article looks in more detail at some of the devices demonstrated in SME and discusses how and where they can improve the performance of military electronics.
The Fundamentals of Superconducting Logic
SME uses critically damped Josephson junctions as it's basic element; arranging them into flip-flops, registers, memory cells, sampling circuits and logic gates to form a superconducting version of almost anything that can be made with a transistor. The parts of most interest today fall into two broad categories:
Digital radio parts such as data converters, digital mixers and digital filters for use in truly all-digital radios (digital right from the antenna connector). Logic functions for ultra-high-speed signal processing chips.
Named after physicist Brian Josephson, who first described their operation,1 Josephson junctions are formed when two superconducting layers are separated by a thin insulating layer. The physics of their operation is beyond the scope of this article, but the behavior of the electrons on both sides of the insulating barrier is closely correlated, leading to useful non-linear behavior in many instances. Most relevant to SME is the observation that, when voltage is applied to a superconducting loop containing a Josephson junction, magnetic flux can only enter the loop in discrete amounts, each corresponding to an integer number of "fluxons" (the magnetic analog of the electron). The fluxons will remain there until something stimulates them to leave.
The mid '90s brought a dramatic development in superconducting logic technology which rescued it from the 1 GHz clock speeds thought to be the limit of Josephson junction-based logic.2 This new logic was known as "rapid single flux quantum logic" and brought the prospect of 200 GHz integrated circuits. Digital 1s and 0s are stored as fluxons contained in superconducting loops fabricated from Niobium films deposited onto silicon wafers. The silicon is simply a physical carrier for the Niobium film, which is deposited on it using low-cost vapor deposition techniques. The silicon wafer plays no part in the behavior of the circuit and can be polycrystalline and even chemically contaminated, leading to very low fabrication costs, even for future sub-micron feature sizes.
Superconducting logic combines Josephson Junctions into traditional circuit elements, with flip-flop circuits forming naturally from the built-in memory (inductance in a superconducting loop can store magnetic flux indefinitely, hence forming an integrated memory cell). Digital 1s and 0s are the presence or absence of a stored flux quantum (fluxon) in the storage loop shown in Figure 1.
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Figure 1. Diagram showing the clock pulse stimulating the emission of a flux quantum on the OUT line - if one is stored in the storage loop at the time. "X" is the standard symbol for a Josephson junction.
Fluxons move around the circuit as picosecond pulses of magnetic flux (called "SFQ" pulses). A pulse on the clock line causes a fluxon stored in the part of the circuit (labeled "storage loop" in Figure 1) to be emitted to the following circuit stage because it exceeds the critical current of the lower Josephson junctions ringed in red. If no fluxon is present in the loop at the time the clock pulse is asserted, no fluxon will be output. In this way, large circuits can be synchronously clocked. Locally synchronous, globally asynchronous operation can also be supported in large circuits.
More complex logic elements can be built from the basic building blocks as shown in Figure 2. Arrows indicate the clock pulse entry point.
Furthermore, these magnetic fluxons, the magnetic analog of the electron, are almost unaffected by charged particles or gamma rays. This means superconducting devices are inherently tolerant to high radiation environments and have been shown to operate quite normally in a 6.5 MeV proton fluence of 1016 pcm 2. This offers the prospect of loading computing power into satellites and designing battlefield systems able to function in high-radiation environments.
Taking the all-digital radio first, SME ADC chips are the only parts able to directly digitize multi-GHz signals (at high resolution) and digitally filter the resulting massive data stream down to a rate that can be handled by conventional electronics. Figure 3 shows a 15-bit lowpass ADC. A development of this part was recently delivered to the U.S. Navy with a SINAD of > 121 dBc at 400 kHz. This is substantially better than any other ADC known to the authors.
Furthermore, in 2006, a second generation of RF frequency ADCs with upgraded digital filtering and SNRs > 75 dB over 40 MHz bandwidth and directly sampling carriers between 1 and 5 GHz (without analog mixers) are expected, with even further performance upgrades to follow.
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Figure 2. Circuit elements of increasing complexity can be formed from the basic elements.
A key difference between SME and conventional silicon ADCs is the absence of the capacitor-based sample-and-hold circuit in SME. This removes the uncomfortable trade-off between a circuit good for high bandwidth and one good for linearity. The result is that most SME-based ADCs use the sigma-delta architecture used in low-frequency/high-linearity semiconductor ADCs, but extend the raw sample rate to tens of GHz, allowing the designer the flexibility to trade bandwidth for resolution at any time in software, and on GHz signals.
Once the waveform has been captured, high-speed SME logic is used to implement a numerical mixer and filter to bring the signal down to the bandwidths and frequencies that can be handled using conventional electronics.
On the transmit side, the speed of superconducting signal processing offers the prospect of direct RF synthesis PAs. These offer valuable increases in efficiency and bandwidth over the current narrowband "waveform amplifiers" in use today. In this way, every aspect of the waveform can be controlled and adapted in real-time using software.
The computing power now applied to filtering the output data streams of superconducting ADCs can also be put to use processing data in other ways. The heat produced when superconducting circuits switch is between three and six orders of magnitude lower than that produced by state-of-the-art transistors, and the signals passed between devices are single quanta of magnetic flux so there is no need to pump charge through ever-shrinking wires to feed the capacitance of the next transistor in the circuit. This effectively removes the well-known thermal problems now limiting the speed of silicon ICs to around 4 GHz. This, and the speed with which signals can be propagated across a superconducting chip, has allowed complex VLSI circuits to be developed, clocking at speeds of 40 GHz (even at the 1.5 µm fabrication node). Smaller-scale devices have been clocked as high as 750 GHz, and as the fabrication nodes used follow the semiconductor industry into the sub-micron range, these numbers will continue to rise.
The Road from Physics to the Battlefield
There are many problems that must be solved before promising physics can become a fully functional IC technology; but, one by one, these have been solved in superconducting logic. Interfaces to the outside world must be developed, clocking and timing techniques must be robust and chip fabrication must be understood to the extent that clear design rules can be given to circuit designers. These design rules must result in good manufacturing yields even for die with many thousands, and eventually millions, of junctions on them.
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Figure 3. High performance A/D converter implemented in SME platform.
A difficult problem for superconducting logic in the past has been memory. The current 1.5 µm lithography resolution makes memory cells physically large, and at a 40 GHz clock rate, this size can slow memory access if the element to be accessed is at the wrong side of the RAM array. This problem will diminish as smaller fabrication nodes are brought on stream. But in the meantime, sophisticated memory caching techniques have been developed to keep effective memory performance high, where bulk data storage must be supplied access to conventional silicon memory runs as high as 30 Gwords/s.
Another important innovation in superconducting logic is the ability to produce high-frequency, high-Q oscillators directly on-chip. This satisfies the need for precision low-jitter clocks for ADC components and makes the provision of a clock source for 40 GHz circuits relatively easy and transparent to the circuit designer. Published data shows an on-chip oscillator with a cycle-to-cycle jitter as low as 5 fs, indicating a resonator Q of almost 5,000,000.3 A master clock can be fed onto the chip to synchronize the oscillator to other system circuits, using a conventional PLL architecture where desired. All the digital components of the PLL are implemented in superconducting logic, leaving only the simple loop filter components to be placed off-chip. Further developments should enable these to be integrated in many situations too.
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Figure 4. Typical pulse tube cooler.
A good example of the power of these superconducting DSP circuits is the development of a chip for multi-user detection in CDMA mobile wireless systems.4 This is known to be a difficult problem in digital signal processing, and will be a powerful example of the way superconducting logic has matured to the point where it can solve key technical challenges facing the military electronics designer today.
Once the Achilles heel of superconducting electronics, cooling technology has matured to deliver compact and reliable units that are operating every day in satellites, semiconductor fabs and even commercial cellular basestations across the world. In cellular basestations, cumulative runtime by the end of 2003 was in excess of 38 million hours, with only two devices known to have failed for any reason. A typical single-stage pulse-tube cooler is shown in Figure 4; dual-stage coolers capable of cooling SME parts to 4k are only slightly larger.
Research projects are in progress, looking for an all-solid-state cooling solution which will provide the next substantial drop in system size, weight and power.
The military field is full of requirements for high performance signal processing, and a technology capable of capturing and manipulating signals seamlessly in the digital domain is attractive. A 40 GHz processor enables a new generation of digital processing technology thought impossible until now. Below are some current programs and examples of ways in which superconducting electronics could improve their performance.
Signal intelligence Sensitive, wideband, fast sampling receivers are a key requirement for signal intelligence applications. Huge swathes of spectrum can be monitored simultaneously with fast sampling ADC devices which, when coupled to 40 GHz digital correlators, enable the detection of new ultra-wideband secure transmission systems. In addition, the zero resistance front-end and low temperature of the ADC makes superconductor electronic systems the most sensitive receivers available. They are commonly used in radio astronomy systems today.
On the transmit side, signal spreading circuits are similarly fast and enable the bandwidth of ultra-wideband waveforms to be extended by an order of magnitude.
MUOS and other MilSATCOM applications Moving to more conventional bandwidths, the MUOS program will provide Internet generation connectivity to the battlefield, using 3G mobile technology, by placing five satellites into geostationary orbit and upgrading existing capacity by a factor of 10.5 Superconducting technology is particularly well-suited to satellite communications. Some of the advantages are outlined below.
With the advent of GHz-frequency ADCs, the unique sensitivity of superconductor electronics can now be applied to satellite communications. Any improvement in the noise performance of the satellite front-end directly leads to a reduction in the transmit power required of the soldier's radio. This enables a dramatic reduction in the size of portable radio equipment or an increase in its operating time. Both features are of great benefit to a soldier in battle, as well as other satellite-based communication systems.
Superconducting front-ends have a very high dynamic range as high as 122 dBc SINAD and impressive specifications are also available in GHz-sampling devices. This gives the satellite receiver greatly improved jamming resistance in the face of hostile attack.
Superconducting chips work by moving magnetism around, not charge. This gives them great resistance to radiation in space, enabling radiation-hardened chips for data processing in the satellites.
Advanced multi-user detection and interference cancellation systems are made possible by the speed of superconducting processors. This has been shown to give system capacity increases as high as 70% in 3G mobile wireless systems.6 Similar capacity benefits or increased immunity to hostile jamming should be available to military systems using the same technology.
The space environment provides a side benefit for superconducting logic: it's cold out there. As previously discussed, coolers are routinely used in space and are known for their reliability. The ambient temperature of a satellite is usually between 40° K and 100° K (out of direct sunlight), making the workload of a cooler much smaller. As a result, superconducting ICs can be mounted on a satellite with minimal launch weight penalty.
JTRS This project has had some well-publicized problems recently, but at least some of them could probably be managed by using superconducting technology. DSP chips, operating at 40 GHz, provide sufficient processing power to handle complex waveforms, and the flexible digital front-end is a much more elegant method of handling the multitude of transmit and receive frequencies that JTRS is required to support. Highly efficient, wideband PAs are being developed to enable the frequency agile transmission needed to close the communications loop.
There are several DARPA programs that would benefit both from the speed and integrated nature of digital RF and superconductor microelectronics. One example is a program which seeks to develop ad-hoc wireless mesh systems where individual nodes constantly listen for transmissions by other units, receive them, decode them and retransmit them in cooperation with the source node to enhance the signal received at the final destination. Current systems do this on a frame-to-frame basis (milliseconds), but DARPA seeks to extend this down to bit level, which requires a whole new generation of hardware. Digital RF may be the only viable option.
DSP algorithm development is one of the most vibrant areas of research in wireless communications. Current implementations are burdened by the need to parallelize most problems, due to the slow clock speed of current devices. Adding a factor of 10 to the processor speed will release a whole generation of algorithm developers to concentrate their energies on problems of more direct benefit to the military, aerospace and security industries.
1. Josephson, B.D. Phys. Letters1, 251 (1962).
2. Mukhanov, O.A., V. K. Semenov and K. K. Likharev. "Ultimate Performance of the RSFQ Logic Circuits. " IEEE Trans. Magn., vol. MAG-23, No. 2, pp. 759-762, Mar. 1987.
3. Kirichenko, D.E. and I.V. Vernik. "High Quality on Chip Long Annular JJ Clock Source. " IEEE Trans. Appl. Supercond. Vol 15, No. 2, pp 296-299, Jun 2005.
4. Kataeva, I., H. Engseth and Kidiyarova-Shevchenko, Anna. "RSFQ DSP for Interference Cancellation." IEEE Trans. on Appl. Supercond., vol. 15, no. 2, pp. 405, Jun 2005.
5. http://www.isrjournal.com/story. php?F=451795.
6. Gunnarsson, F & B. Hagermann. "System Aspects of WCDMA Uplink Parallel Interference Cancellation." IEEE Signal Communications. To be published.
About the Author
Christopher Hole, PhD, vice president of business development/chief system engineer, joined HYPRES in 2005. He has more than a decade of experience in superconductivity and wireless communications. Dr. Hole earned his PhD studying superconductivity in ultra-high magnetic fields at the University of Oxford, UK, and was a Royal Society research fellow at the National Research Institute for Metals, Tsukuba, Japan. Moving to the commercial sector, Dr. Hole held research and design positions at Oxford Instruments, where he worked on developing next generation high-field research magnets, and at REMEC, where he worked on the design and system architecture of wireless basestations.