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Chip-optimization Technology

Thu, 03/02/2006 - 7:00am

Cadence announces its manufacturing-aware chip optimization product Cadence® Chip Optimizer, a silicon-proven full-chip optimization system. Cadence Chip Optimizer is used after conventional place and route and before design tape-out. The product uses a 3D space-based optimization approach which models, analyzes and optimizes true shapes and intervening physical spaces. This provides a realistic "map" of the design, and indicates where important optimizations may be made. Shapes and spaces can be positioned in the configuration and location required to correct for sub wavelength, spacing and topological effects.


Cadence Design Systems


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