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Upgrade to SoC Verification Technology

Thu, 02/02/2006 - 9:20am

Cadence Design Systems announces an upgrade to its system-on-chip (SoC) verification technology with the Cadence® Incisive® Enterprise Specman Elite® 5.0 test bench automation solution with tight integration to the Incisive Enterprise Specman Simulator. Developed to serve multiple specialists, Specman Elite 5.0 provides up to three times greater run time and 60% greater memory performance than previous versions, with enhanced usability and improved scalability of generation and coverage. With the addition of 64-bit support for the Intel EM64T and AMD Opteron platforms with RHEL 3 or SuSE 9 Linux, Specman 5.0 addresses the growing demand for larger memory footprint capabilities that cover simulations run in full-chip and system-level verification. Improvements in functionality include enhanced full-system transaction modeling support with advanced options for connecting the test bench and design under test (DUT) to improve performance and code reusability and improved user interface that simplifies the debug process. Enterprise Specman Elite 5.0 enables users to improve the quality of their end products while further shortening the entire verification cycle.


Cadence Design Systems, Inc.


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