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Software Aids SystemVerilog Adoption

Thu, 12/08/2005 - 6:11am

Cadence Design Systems, Inc. introduces the Incisive® Design Team family, tailored for RTL design teams looking for a low-risk, yet powerful way to adopt SystemVerilog-based verification from plan to closure. The product family leverages proven verification process automation (VPA) methodologies, technologies, and management solutions from the company’s acquisition of Verisity. Part of a new three-tiered Incisive platform, the Incisive Design Team family includes broad SystemVerilog language support, new product integrations, and tightly coupled methodologies optimized for design teams tasked with RTL verification. The family includes: Incisive Design Team Manager, a new version of the Incisive Verification Manager for SystemVerilog and VHDL-based verification management; Incisive Design Team Simulator, enhanced with new SystemVerilog test bench extensions, comprehensive SystemVerilog assertion (SVA) support, and integration with the Incisive Design Team Manager; Incisive Design Team Xtreme Server, simulator-like acceleration and emulation solution; Incisive Design Team Formal Verifier, optimized for design team use prior to test bench availability; a packaged plan-to-closure methodology, tailored for RTL design teams adopting SystemVerilog for verification.


Cadence Design Systems, Inc.


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