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Radio Transceivers Using an I/Q Receiver Interface

Thu, 12/08/2005 - 6:07am

By C.N. Wilson

Conventional FM receivers use an analog demodulator, such as a PLL, or more commonly, a limiter-discriminator. Digital schemes replace these with digital processors. The following information covers general issues involving digital demodulators, with the marine AIS as an example. Various CML ICs are cited, in particular the CMX910 as used for marine AIS; but the technology and methods described suit many other data transfer interfaces.

AIS is a data signaling system that uses a version of TDMA known as SoTDMA. The modulation used is GMSK/GFSK at a data rate of 9,600 b/s in 12.5 kHz or 25 kHz channels.

The transmitter modulation can be developed by either a digital modulator or by traditional analog methods as shown in Figure 1. In theory, the scheme in Figure 1 can also be used to generate MSK, but this relies on a known, fixed VCO gain. Thus, in analog implementations of this scheme, MSK modulation is not practical. To make this analog scheme practical, the VCO is usually part of a PLL that controls the VCO’s frequency. Modulation can be applied directly to the VCO or, if data has significant DC content, two-point modulation can be used where both the VCO and the PLL reference are modulated.

It follows that AIS modulation has much in common with traditional FM for voice communications. In fact, the modulator is typical of FM communication systems. Although conventional FM receiver structures maybe used for this data system — and indeed the classic limiter-discriminator architecture has been adopted in a number of AIS designs — digital demodulators offer some advantages to wireless data systems.

Receiver architectures for AIS wireless data systems fall into digital and analog categories. For our purposes, the difference is whether FM demodulation is performed by analog means, or digital, within a DSP, for example.

Analog demodulator— The analog approach, using a classic limiter-discriminator, is shown in Figure 2. In this scheme, the received signal is amplified in a way that removes amplitude variation caused by the RF path. The resulting signal is delayed and mixed with the original signal to give a difference-signal output: This represents the frequency or phase modulation in the incoming signal. This is differential detection, and the circuit is widely known as a discriminator.

Following the discriminator, the modulation looks like an analog data stream, but to recover the data, the bit-timing must be ascertained and a decision must be made whether the signal, at any particular instant, represents a "1" or a "0." The data recovery is done by some method of "data-slicing," followed by a timing recovery circuit. In advanced schemes, to optimize the two, these functions may be closely linked. The data recovery mechanism is critical because the output of the analog discriminator can sit on a varying DC level. The data slicer circuits must deal with this to ensure that errors are not introduced into the data as a result of this variation whatever its source; e.g., slight frequency shifts in the receiver, temperature effects and drift in the discriminator tuning.

The analog scheme is well-proven, but it has two points where, for digital (data) modulation, it can have drawbacks. The first is the need to deal with DC drift in the demodulated output. The second, and probably more important, is the need to implement all receiver filtering prior to the limiter. This means that analog filters must be used to achieve adjacent-channel rejection. These have the obvious disadvantages of size and cost and also present the subtler problem, in digital systems, of group delay distortion. This is an important factor that will be considered in further below.

The I/Q approach is probably the more widely adopted because it can offer lower power consumption and lower cost and so, for the purposes of this discussion, we will not consider IF sampled schemes further.

The demodulator structures for digital systems using G(M)FSK are the same as for the analog schemes, except they can be implemented within a DSP IC (see Figure 3). Once sampled, the I/Q signals need to be demodulated in some form of digital discriminator. Then, the data are recovered using some kind of data slicer and timing recovery.

The digital scheme has a number of subtle advantages, but its big improvement is the ability to provide digital filtering of the signal prior to the discriminator function.

Demodulator Technology Issues

Adjacent channel filtering— The way adjacent channel filtering is achieved in digital and analog receivers differs greatly, but in both, all channel filtering must be carried out prior to the discriminator. This is essential because the discriminator treats any interfering signals present at its input the same as the desired signal and demodulates them all. As a result, with a large interferer, the wanted data can not be recovered. The analog scheme relies on the signal being at a constant amplitude prior to the quadrature mixing to recover the modulation; hence the use of a limiter as seen in Figure 2. This requires adjacent channel rejection prior to the limiter.

In the analog scheme, all channel filtering must be implemented as analog filters. In practice, this filtering is generally a combination of crystal filters in the first IF and ceramic filters at the second IF. These filters are relatively large and expensive. Furthermore, the filters require careful matching to ensure optimum characteristics are achieved. Temperature and aging can cause the filter response to vary, affecting the receiver’s overall performance.

Some typical 4-pole crystal filter responses are shown in the following plots. Figure 4 and Figure 5 show the response of a well-tuned filter designed for 12.5 kHz operation (e.g. AIS class A 12.5 kHz mode). The group delay response is not particularly flat in the passband; but with a slight misalignment, the group delay looks like that of Figure 6. Figure 7 shows typical crystal filter characteristics for 25 kHz channels.

A study of the filter responses shows that it is difficult to achieve the AIS-specified adjacent channel rejection with crystal filters alone. The problem is that the roll-off is just not steep enough to remove the adjacent channel power in the part of the adjacent channel closest to the desired signal. To achieve the required rejection, ceramic filters are generally used in a second IF, typically 455 kHz or 450 kHz. Figure 8 shows the typical performance of such a filter.

Both crystal and ceramic filters exhibit significant group delay ripple, as can be seen in the various plots. In analog voice systems, this ripple can be tolerated without any problem; but in digital systems, this will distort the digital signal resulting in a higher error-rate in the receiver.

To show the effect, consider the received signal prior to the data slicing but after the data filter. This signal, when displayed on an oscilloscope, is known as an eye diagram. The plots of Figure 9 and Figure 10 show the results from a receiver with (Figure 10) and without (Figure 9) a crystal filter. The input power in both plots is – 100 dBm, well above a nominal sensitivity of – 115 dBm. Figure 9 shows a clean "eye" with well-defined zero crossings; however in Figure 10, the phase distortion introduced by the filter causes both a closing of the "eye" and significant jitter on the zero crossings. The result in the receiver under test was that the measured sensitivity for a 1% BER was degraded by 4 dB with the crystal filter in-circuit. These tests showed that the filter was too narrow for the particular system and that a wider design with better group delay was required.

Figure 1. G(M)FSK modulation generation. Figure 2. Limiter-discriminator analog demodulator. Figure 3. Digital discriminator radio architecture. Figure 4. Frequency response of typical crystal filter used for 12.5 kHz systems. Figure 5. Group delay characteristic of typical crystal filter (as shown in Error! Reference source not found.). Figure 6. Group delay characteristic of typical crystal filter when slightly misaligned (same filter as in Error! Reference source not found. and Error! Reference source not found.). Figure 7. Phase and frequency response of typical crystal filter for 25 kHz receiver. Figure 8. Typical ceramic filter used at 455 kHz IF for 25 kHz receiver (±7.5 kHz passband). Figure 9. Eye diagram from GMSK receiver (Bt = 0.3) with no IF crystal filter. Figure 10. Eye diagram from GMSK receiver (Bt = 0.3) with crystal filter.


ADC— Analog-to-Digital Converter

AGC— Automatic Gain Control

AIS— Automatic Identification System

BER— Bit Error Rate

C/I— Carrier-to-Interference

C/N— Carrier-to-Noise

C4FM— Constant Envelope 4-Level Frequency Modulation

CS— Carrier Sense

CS-TDMA— Carrier Sense-Time Division Multiple Access

DAC— Digital-to-Analog Converter

DSP— Digital Signal Processor or Digital Signal Processing

FIR— Finite Impulse Response

FSK— Freuqency Shift Keying

GFSK— Gaussian Frequency Shift Keying

GMSK— Gaussian Minimum Shift Keying

I— In-Phase

IC— Integrated Circuit

IF— Intermediate Frequency

MSK— Minimum Shift Keying

PCB— Printed Circuit Board

PLL— Phase-Locked Loop

Q— Quadrature

RSSI— Received Signal Strength Indication

Rx— Receive

S/N— Signal-to-Noise Ratio

SoTDMA— Self-Organizing TDMA

TDMA— Time Division Multiple Access

TETRA— Terrestrial Trunked Radio (formerly Trans European Trunked Radio Access)

Tx— Transmit

VCO— Voltage-Controlled Oscillator


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