Product Releases

Radio Transceivers Using an I/Q Receiver Interface: Part II

Fri, 12/30/2005 - 7:52am

Part II concludes the examination of demodulator technology and presents the rest of the technical discussion.
By C.N. Wilson

Glossary of Acronyms

ADC — Analog-to-Digital Converter AGC — Automatic Gain Control
AIS — Automatic Identification System
BER — Bit Error Rate
C/I — Carrier-to-Interference
C/N — Carrier-to-Noise
C4FM — Constant Envelope 4-Level Frequency Modulation
CS — Carrier Sense
CS-TDMA — Carrier Sense-Time Division Multiple Access
DAC — Digital-to-Analog Converter
DSP — Digital Signal Processor or Digital Signal Processing
FIR — Finite Impulse Response
FSK — Freuqency Shift Keying
GFSK — Gaussian Frequency Shift Keying
GMSK — Gaussian Minimum Shift Keying
I — In-Phase
IC — Integrated Circuit
IF — Intermediate Frequency
MSK — Minimum Shift Keying
PCB — Printed Circuit Board
PLL — Phase-Locked Loop
Q — Quadrature
RSSI — Received Signal Strength Indication
Rx — Receive
S/N — Signal-to-Noise Ratio
SoTDMA — Self-Organizing TDMA
TDMA — Time Division Multiple Access
TETRA — Terrestrial Trunked Radio (formerly Trans European Trunked Radio Access)
Tx — Transmit

The group delay variation caused by analog filters can be avoided by using a digital filter. The FIR filter implemented has a constant group delay resulting in a linear phase response, as shown in Figure 11. When the AIS received data is passed through this filter there is no degradation of the sensitivity or jitter introduced in the zero-crossings. The FIR filter also provides excellent rejection of the adjacent-channel signal; greater than 60 dB is achieved. This rejection means that the IF ceramic filters are not required. Typically, however, a crystal filter would still be used in the first IF stages to limit the dynamic range presented to the ADC, however rejection requirements are somewhat relaxed compared to an analog design.

The net result: by minimizing the analog filtering requirements, the digital approach can save PCB area, reduce material costs and improve sensitivity and co-channel performance.

The improvement in co-channel performance may be surprising, but it results from the improved group delay. Group delay variation has been demonstrated to cause jitter in the zero-crossings. In the presence of noise, this would make the demodulator's ability to recover bit timing more difficult.

The signal training information in AIS systems is relatively simple compared to some similar systems — a series of 11001100 followed by 01111110 (7EH) — a sequence not ideal for timing recovery by correlation, for example.

Thus, any distortion that makes timing recovery more difficult is likely to have a negative affect on packet error-rate performance close to C/I or C/N limits.

Filter design for a digital receiver— To optimize the receiver filtering, it is necessary to consider the amount of rejection required from each filtering stage. With a digital interferer, it is necessary to calculate the rejection of that signal by applying the filter response to the modulation spectrum. This can either be done by one of the many available system simulation tools or by a spreadsheet that can be used to perform a piece-wise analysis of the rejection. An example is shown in Figure 12 for the rejection requirement using C4FM modulation passed through analog filters (crystal) and then digital filters (using CML's digital radio baseband processor IC — the CMX981).

click the image to enlarge

Figure 11. FIR filter response in I/Q channels of CMX910.

The analog filter is relatively wide and thus provides little degradation of passband characteristics. The attenuation achieved is enough to limit the dynamic range of the signal so that minimum power consumption is required for I/Q downconverters. This also limits the dynamic range required on the ADC, reducing the need for AGC and improving signal-to-noise margins.

In this example, the target was 69 dB rejection of the adjacent channel. Tight filtering of the channel is required because of the amount of adjacent channel modulation that leaks into the desired channel. Increasing the absolute rejection of the FIR filter has practically no effect on the resultant power after the filter. This is clear from Figure 12: With the signal in the adjacent channel well-suppressed (<𤹤 dB), the majority of the power that is left is close to the desired signal passband.

The response of the FIR digital filter (Figure 12) is much sharper than the analog filter, thus achieving an adjacent channel rejection that would be difficult to achieve with analog filters without introducing excessive distortion in the passband.

click the image to enlarge

Figure 12. Analog and digital filter attenuation of C4FM modulation.

The results of the calculations, shown graphically in Figure 12, are given in Table 2. Table 3 shows a proposed partition for receiver filtering using these results.

Dynamic range— The dynamic range of the ADC limits the amount of filtering that the digital section can perform. The ADC must sample both the desired and the undesired signal within its converter range. If the undesired adjacent channel exceeds the input range of the converter, it is likely that the desired information will be degraded. This subject receives more attention below.

Dynamic range partition— In a digital demodulator, the received signal is sampled by an ADC, so the dynamic range of that converter needs to be considered when designing the RF system.

An example dynamic range partition is shown in Figure 13 assuming an ADC with a maximum input signal of 600 mVrms, which is +8.6 dBm assuming a 50Ω input impedance (the actual impedance of the converter is unlikely to be 50Ω but this value is used for convenience). A typical design methodology is to consider the range from top and bottom, leaving an operating window in the middle.

click the image to enlarge

Table 1.

The bottom of the dynamic range is the minimum signal level that the ADC can quantize; this will be where quantization noise occurs, and it is necessary to prevent it from degrading overall receiver performance to ensure that the desired signal is well above that quantization noise. This is achieved by allowing some margin between the noise floor of the signal at sensitivity and the bottom of the converter: 10 dB is a typical figure that ensures a negligible effect on the sensitivity from quantization noise. To calculate minimum signal level, the C/N of the receiver must be added to the thermal noise. When the precise C/N of a modem is not known, the C/I value from the product standard is often used.

click the image to enlarge

Table 2.

A further margin can be added to allow for variation in C/N with, for example, frequency offset, filter variations, etc. In Figure 13, this results in a minimum input signal to the ADC of – 53.4 dBm.

The maximum operating signal level is set by the level of filtering that the baseband FIR filters are to perform. The example assumes an objective of attenuating a signal 35 dB above the desired signal. It is also prudent to allow some margin on the maximum signal, for example, 3 dB as shown. This then sets an upper limit on a desired signal that can be presented when an adjacent channel interferer is expected.

It should be noted that the selection of some of these parameters is affected by a number of considerations. For example, the filtering requirements for the receiver as a whole must be balanced with the ADC dynamic range.

click the image to enlarge

Figure 13. ADC input dynamic range partition.

Rx Path Gain— Given the partition shown in Figure 13, the total receiver gain can now be calculated. Units of dBm are used for simplicity in these calculations, although the actual impedance at the ADC input will not be 50Ω. Using the power equivalent in 50Ω means that gains through the receiver chain can be evaluated independent of impedance. The net result is the establishment of a voltage-gain plan. Real voltage can be determined based upon 50Ωat any point and power determined from actual impedance. The following assumptions are used in this calculation:

• Interferer measurements are at 3 dB above the sensitivity limit.

• Best case receiver sensitivity is 𤩨 dBm.

• Worst case receiver sensitivity is – 110 dBm.

Minimum gain can be calculated as:

Minimum operating point of ADC = – 53.4 dBm Minimum input level (maximum sensitivity) = 𤩨 dBm Minimum Rx Path (voltage) gain = 66.6 dB Maximum gain can be calculated as: Maximum operating point of ADC = – 29.4 dBm Maximum input signal level at sensitivity = 𤩞 dBm Degradation measurement level = 3 dB Maximum Rx Path (voltage) gain = 77.6 dB

This leaves an 11 dB window in which to set the nominal gain of the receiver. A nominal value may be, for example, 72 dB.

Gain Control Range— Digital receivers often use AGC to ensure a wide linear dynamic range. This is essential for linear modulations where amplitude is a component of the signal. For G(M)FSK systems this is not strictly necessary because these are phase/frequency modulations, and no information is contained in the amplitude. As a result, the AGC stage shown in Figure 3 is not strictly necessary. In this case the RF designer should pay careful attention to the levels through the receiver and ensure that compression and limiting both occur at appropriate points. It is essential to ensure that the ADC does not over-range, so compression in an analog stage should be arranged to prevent such problems. Furthermore, compression in mixers can often be problematic, giving rise to spurious responses, so compression in an IF amplifier stage is often a good way to achieve a simple, high-dynamic range digital system.

click the image to enlarge

Figure 14. DC-offset correction scheme.

Moreover, it is sometimes helpful to have a simple AGC arrangement, maybe only one step. This allows the gain to be reduced and ensures that compression occurs well away from the level of an adjacent-channel interferer.

Dynamic range and filtering— The filtering achieved by an FIR filter in the receiver is only usable if the ADC can sample a desired signal and interferer such that the attenuation can be applied. The filter typically rejects the desired signal by more than the headroom allowed in the dynamic range partition.

This effect is best explained using an example of the AIS processor filter response in Figure 11. This shows that the FIR will reject an interferer at a 25 kHz offset by more than 70 dB. If the dynamic range partition shown in Figure 13 is used with this filter, and the AIS-specified interferer at 60 dB above the desired is applied, the ADC will be driven into saturation, and the desired data is likely to be destroyed.

Correct operation of the system would be to limit the signal applied to the ADC to 35 dB above the desired signal (by using filtering in the first IF). The digital filter will now reject the adjacent signal to about 35 dB below the desired signal, allowing the demodulator to recover the desired signal correctly.

The operating window (Figure 13) gives a range over which the full adjacent channel rejection of the receiver can be maintained, and AGC can be used to maintain the signal within the operating window. However, adjacent channel selectivity is typically only tested close to sensitivity. This means that the signal can be allowed to rise up the converter range, degrading adjacent channel rejection in relative terms, although the absolute level of any interferer remains the same (at least until the desired signal reaches level similar to the interferer where the composite signal may exceed ADC input range).

DC offsets DC offsets can cause problems within an I/Q digital architecture, so steps are required to prevent such problems. As the signal is mixed to baseband, some DC will be present; this will be captured by the ADC as the signal is converted to the digital domain. Because the received signal may be small, maybe a few mV, and any level of DC needs to be well below the signal level, the tolerable DC offset is generally quite small. Such small levels are easily generated by any imperfection in even the best-designed analog mixers and amplifiers.

click the image to enlarge

Figure 15. Example of analog CS-TDMA threshold detection system.

DC-offset removal— To remove the DC offset, a number of techniques can be used. Averaging the received signal and removing the DC can be an effective solution; however, great care is needed with such a scheme because the modulation content of the received signal can affect the result. Also, if averaging over a short time is used, the desired signal can be distorted by the DC removal, resulting in poorer S/N performance. Averaging over a long time can also be problematic; for example, if short burst signals are to be detected, the averaging may not have reached the optimum level when data starts to arrive. DC-offset removal is therefore best considered knowing details of the signal to be received.

If initial DC calibration can be performed in the presence of noise (no signal), then averaging can be much faster because the potential DC content of the data can be ignored. This allows a rapid measurement of the DC offset. To ensure that no signal is present, it is often beneficial to arrange that some sections of the RF circuitry can be isolated or powered down — however, clearly it is essential that circuits that may contribute to the DC offset are undisturbed.

An example of this scheme, as implemented in the CMX990, (GMSK baseband processor with RF support) is shown in Figure 14.

As will be seen, this particular circuit can be put into an I/Q DC-offset acquire mode during which the first stages of the receiver are disabled. The IF and I/Q circuits remain powered, and a rapid measurement of DC offset is made. When normal operation is enabled, the measured DC offset is automatically subtracted from the data, resulting in effective DC offset removal.

The CMX910 (AIS) does not include RF circuits but provides similar DC offset removal facilities to those of the CMX990, with a fast averaging mode intended for rapid measurement of DC levels from the receiver in the absence of signal. A further mode is provided that is intended to track DC changes that occur during normal operation of the receiver. For example, a change in temperature may cause a shift in DC level. Such changes will occur during a relatively long period (compared to the symbol rate), so a slower averaging mode is appropriate. Knowing that the AIS signal is bursty in nature, and it is likely that there will be variations in signal levels and gaps between bursts, using an intelligent averaging scheme. Given this knowledge, measured samples can be weighted in significance optimizing DC tracking performance. The net result is that the processor is particularly effective in dealing with the problems of DC offsets.

Once the DC content of the modulation is removed, the modem can use something close to the full range of the ADC converter.

AC coupling— One apparently simple solution to DC offset problems is to AC-couple the baseband signal to the ADC. The problem with this action is that long sequences of 1s or 0s could be corrupted because of the data decaying with the time constant associated with the coupling capacitor. For the AIS system, bit stuffing is used to limit the maximum run length in the data; therefore, it would appear that AC coupling is a practical solution.

Unfortunately, things are not that straightforward. The maximum length of continuous 1 or 0 s in AIS is six bits (in the start flag 7EHex), so drop should be designed to be insignificant over a period of 625 µs, suggesting a time constant of several milliseconds. The problem comes because, in the case of AIS data, the signal is bursty in nature, and a strong signal received in one AIS time slot can be followed by another much weaker (at sensitivity), from a different transmitter. If AC coupling is used, the large signal may still be decaying when the weaker signal in the next slot arrives, causing a DC slope on the signal that is difficult to remove. The result is that AC-coupled systems have been found to have practical problems that make them difficult to use in AIS equipment.

Carrier Sense — TDMA and RSSI— The AIS Class B system uses a CS-TDMA system for channel access. This system relies on a short turnaround time between Tx and Rx; in fact, only four bits (416 µs) are allowed for the on-air sensing window and the start of Tx. This time must include processing delays and analog delays through the receiver. As shown in Figures 7 and 8, the delay through analog filters is typically 50 µs per filter. With multiple ceramic and crystal filters in an analog solution, the delay may be nearly 150 µs, leaving only 266 µs for sensing, processing delays and physical Tx/Rx switching. The threshold at – 107 dBm is the same as the receiver sensitivity, so the signal is reasonably close to the noise level. Using a simple threshold detector could have noise immunity issues; therefore, some averaging is recommended.

The CMX910 (AIS) digital system has been specially designed to cope with CS-TDMA operation with access to raw ADC data prior to filtering delays. This allows the maximum window for averaging, and hence, accurate CS-TDMA decisions.

An integral part of CS-TDMA operation within a digital baseband system is the baseband-measuring RSSI. This places a constraint on the RF hardware in that the gain through the receiver must be well-characterized and relatively temperature-stable. Although this seems onerous, in fact the same requirement applies to an analog demodulator where the designer often has less control of the performance of the circuits. Accurate RSSI measurement is necessary because the carrier sense threshold is adaptive.

In the limiter-discriminator architecture, the RSSI is typically generated as an analog signal from the limiter (log-amp) stages. This must then be used to measure RSSI and make CS-TDMA decisions. An example solution is shown in Figure 15. The analogue signal must be sampled to obtain a digital representation that can then be processed to determine the variable CS decision threshold, as specified in the AIS- class B standard.

The calculated threshold must then be generated from a DAC and used in a comparator to determine if the CS threshold has been exceeded. This scheme could be simplified if the CS threshold evaluation were determined in the host processor. Doing this is relatively straightforward as long as the ADC has a suitable conversion rate and low delay. This means careful selection of an ADC device is essential.


The differences between analog and digital demodulation for data systems has some rather complex implications. An appreciation of the issues will allow designers more confidence in tackling a digital I/Q based solution, allowing them to access the benefits of performance, flexibility and integration.


Functions relevant to several CML Microcircuits IC products are cited throughout this article as by way of operational examples.

These products are:

• CMX910: AIS Baseband Processor IC

• CMX990: GMSK Packet-Data Modem and RF Transceiver IC

• CMX98: Advanced Digital Radio Baseband Processor

About the Author

C.N. Wilson is managing (operations) director of Applied Technology (UK) Ltd., A DSP software and RF engineering company and part of CML Microsystems plc. He is involved in a range of projects in communications focused on IC specification, evaluation and applications, specifically marine AIS system, Mobitex wireless data and TETRA systems. He can be reached at


Share this Story

You may login with either your assigned username or your e-mail address.
The password field is case sensitive.