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Optimization of Sub-100 nm Γ -gate Si-MOSFETs for RF Applications

Fri, 12/30/2005 - 7:52am

The Γ -gate MOSFET offers the advantage of reduced gate resistance, a critical parameter in high frequency circuits. Identifying the optimum Γ-gate extension length from the gate and drain resistance point of view, is an essential design parameter in today's aggressively scaled CMOS.
By Mayank Gupta, V.Vidya, V.Ramgopal Rao, Kun H. To and Jason C.S. Woo

By the end of the twentieth century the world had seen an explosion in the breath and depth of application and devices within the wireless industry. With the increasing popularity of wireless communication systems like cordless phones, wireless modems, and personal communication networks, higher levels of RF component integrations are required to reduce both the size and the cost of wireless products.

While CMOS has been the dominating technology for the base-band chipsets, the latest evolution in CMOS technology, with shorter channels and faster devices, has made MOSFET a viable choice for RF application, especially for the frequency in the low GHz region.2 CMOS technology is attractive because of the low cost, high integration and the maturity of the technology. However, gate resistance in aggressively scaled CMOS technologies must be taken into account and modeled correctly for accurate benchmarking of such CMOS technologies for RF applications. 3-5

Due to the equations in this article a PDF has been made available for you to download.


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