Product Releases

CMOS-based RF Integration in 3G

Mon, 08/01/2005 - 7:16am
Robert Fan

Glossary of Acronyms

2.5G — " Second-and-a-half" Generation Cellular (uses existing infrastructure in otherwise circuit-switched GSM and CDMA networks to add some packet-switched data functions)
3G — Third Generation Cellular, with both packet-switched and circuit-switched domains.
BiCMOS — Bipolar Complementary Metal-oxide Semiconductor
CDMA — Code Division Multiple Access
CMOS — Complementary Metal-Oxide Semiconductor
DCOC — DC-Offset Calibration
DCS-1800 — Digital Cellular Service in the 1710 to 1880 MHz band
DCXO — Digitally Controlled Crystal Oscillators
DSP — Digital Signal Processing
EDGE — Enhanced Data GSM Environment
E-GSM-900 — Extended GSM in the 890-960 MHz band
Gm-C — Continuous-time Transconductor-capacitor
GMSK — Gaussian Minimum Shift Keying
GPRS — General Packet Radio Service
GSM— Global System for Mobile Communications (formerly Groupe Speciale Mobile)
GSM-850 — GSM in the 824 to 894 MHz band
I and Q — In-phase and Quadrature
IF — Intermediate Frequency
IIP2 — Second-order Input Intercept Point
LNA — Low-noise Amplifier
OPLL — Offset-frequency Phase-locked Loop
PA — Power Amplifier
PCB — Printed Circuit Board
PCS-1900 — Personal Communications Service in the 1850 to 1990 MHz band
PFD — Phase Frequency Detector
PGA — Programmable-Gain Amplifier
RFIC — Radio Frequency Integrated Circuit
RX — Receive
SAW — Surface Acoustic Wave
SiGe — Silicon Germanium
SNR — Signal-to-Noise Ratio
SoC — System-On-a-chip
TX — Transmit
UMTS-2100 — Universal Mobile Telecommunications Service in the 1920 to 2170 MHz band
VCO — Voltage-Controlled Oscillators<
WCDMA — Wideband Code Division Multiple Access
WLAN — Wireless Local Area Network

CMOS now offers compelling advantages as a development platform for highly integrated next generation multi mode, multifunction transceivers.

Consumer demand for high-speed services and more functionality in smaller and more affordable handsets and hand-helds is driving the industry to creatively step up to the challenge. The pressure to keep costs down and time to market as short as possible are compelling forces that have manufacturers revisiting mature technologies that can now meet these challenges.

Scaling silicon technologies and integrating key component building blocks, such as the RF transceiver, reduce product size and cost. Stringent performance requirements of cellular standards such as GSM previously either limited RF transceiver integration or compelled the use of alternative technologies such as SiGe BiCMOS or bipolar. Now, the increasing popularity of GSM/GPRS CMOS transceivers has elevated proficiency with CMOS RF technology from an option to a requirement.

Although a CMOS RF transceiver design offers compelling advantages, design engineers must overcome architectural and circuit-design challenges to develop highly integrated multi mode transceivers supporting WCDMA, EDGE and GPRS/GSM standards. Is it worth investing time and effort to develop an RF transceiver in CMOS for multimode applications? The market says yes.

Trend Toward Multi Mode

To accommodate non-uniform cellular infrastructure deployment by operators around the world, handset manufacturers combine multiple wireless cellular technologies (multi mode) in one device to offer "the best-selling solution" for a particular market. For example, an increasing number of handsets come to market supporting EDGE, with backward compatibility with GSM/GPRS services. Likewise, future 3G handsets will support WCDMA modes along with EDGE/GPRS/GSM technologies. Worldwide roaming requires five frequency bands: GSM-850 MHz, E-GSM-900MHz, DCS-1800 MHz, PCS-1900 MHz and UMTS-2100 MHz. A handset designer must consider all of these requirements and meet consumer demand for low-cost, small form-factor products.

Silicon integration and module integration foster multi mode functions. Most multi mode platforms combine independent wireless subsystems. For example, a multi mode phone supporting GSM/GPRS and WCDMA may have an RF system with a GSM/GPRS transceiver, a WCDMA transceiver and a multitude of RF front-end and passive components to support the two RF modes and frequency bands. (See Figure 1.) This approach is the most practical because GSM/GPRS and WCDMA channel bit rates are based on different reference clock frequencies (13 MHz/26 MHz and 19.2 MHz, respectively). Also, conventional GSM/GPRS transmitter architecture, such as OPLL, does not apply directly to WCDMA. In this example, reducing the bill of material count (and cost) of the multimode design requires higher levels of integration and innovative RF design techniques.

Multiple RF Front-end System Integration Solutions

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Figure 1. A typical 3G multimode/multiband RF design using seperate 3G and 2G radios.

A common implementation of the RF front-end design for a quad-band GSM/GPRS system, as shown in Figure 2, uses a highly integrated single-chip CMOS transceiver. An antenna switch module connects to the transmit and receive paths, with receiver SAW filters and associated matching circuits for each GSM band. Transmit paths require at least two PAs: one for the GSM850 MHz and EGSM900 MHz bands and a second for the 1.8 GHz DCS and 1.9 GHz PCS bands.

Many available integrated RF front-end modules can reduce component count and simplify the design. They include modules with power-amplifier and power-control logic functions (PA modules) and transmit modules with PA and switch functions. On the receive side, SAW filter banks and RF front-end modules with switchplexer and receive filters are being made.

Compared to the GSM/GPRS system shown in Figure 2, the more complex front-end design of Figure 1’s 3G multimode system supports both 2.5G and 3G RF signaling. The added duplexer is necessary because WCDMA is based on frequency-division duplex, where the transmitter and the receiver are switched on simultaneously. However, just as with GSM/GPRS, economic scaling will bring integration of front-end components.

Today’s cellular baseband architectures fall mainly into two approaches: either the baseband function is divided into separate analog and digital baseband chips, or a single, highly integrated CMOS SoC device containing both analog and digital functions is implemented. Because each approach has distinct advantages, choosing between the two partitioning schemes depends on factors such as selecting a future integration path for the most cost-effective platform solution.

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Figure 2. Single-chip quad-band GSM/GPRS CMOS trnaceiver block diagram.

Although the single-chip approach saves PCB real estate, using separate analog and digital baseband chips enables the most aggressive path for integration because it isolates the analog baseband function from the "pure" digital circuits making up the digital baseband. Using the two-chip approach also enables the digital baseband to scale to smaller and smaller CMOS geometries, while enabling the integration of other digital CMOS platform components — application processor, image processor and memory, for example.

An emerging trend in baseband architecture is to simply eliminate the analog baseband chip altogether, thus optimizing digital baseband function integration while simplifying the radio-to-baseband chip interface design. This approach calls for using a high-speed digital interface between the radio and the digital baseband. The interface may be defined as either a serial or a parallel interface, each with its own pros and cons. A serial interface reduces the number of pins of the device but increases the chip transistor count needed to implement high-speed buffers. A parallel interface increases pin count, and therefore the package size, but may be more efficiently implemented in silicon.

The current DigRF Standards Body has defined a standard high-speed serial interface specification for 2.5G, as shown in Figure 3, and is in the process of defining the interface for 3G systems. The radio design will increase in complexity when supporting the digital interface. It not only has to perform the conversion from analog to digital domain and vice versa, but also must have the necessary interface logic to handle the digital communication with the baseband. A radio built on CMOS process technology can more easily and cost effectively implement both of these functions, compared to alternative processes.

click the image to enlarge

Figure 3. 2G DigRF interface between the radio and digital baseband.

The CMOS Advantage

CMOS technology offers several advantages for implementing transceivers:

  • CMOS exhibits a lower wafer cost-structure compared to SiGe BiCMOS processes at equivalent process geometry
  • CMOS allows for chip manufacturing at multiple fabs using standard high-volume processes
  • CMOS design can scale to smaller process geometries, according Moore's Law
  • CMOS enables the implementation of digital circuitry for the RF functions, resulting in a design that is highly programmable, features small die size and is highly manufacturable, with excellent robustness and yield due to the implementation of standard logic circuits for RF functions
  • The CMOS transceiver can be integrated with other functions, such as the digRF interface or even the digital baseband functions, to form a single-chip RF and baseband component
  • CMOS is a proven technology for transceiver implementation, demonstrated by the millions of GSM/GPRS, WLAN and Bluetooth radios that have been mass-produced using this process.

Choosing the transceiver architecture for multi mode GSM/GPRS/EDGE/WCDMA handset is a critical decision. The integration of the VCOs, frequency synthesizers, loop filters and DCXOs common in many single-chip CMOS GSM/GPRS transceivers today is of particular importance. This high level of integration helps ensure the best radio performance because these critical functions are shielded from external noise sources.

The receiver must provide excellent amplitude modulation suppression performance in the presence of the GSM/GPRS blockers that have a constant amplitude, as well as EDGE or WCDMA blockers that are amplitude modulated. The most prevalent receiver architectures are low IF or zero IF, where the receiver and transmitter chains are designed to eliminate the need for external IF SAW filters, compared to the traditional superheterodyne design. Direct-conversion receivers directly convert the incoming signal to a low-frequency signal, facilitating the implementation of programmable filters. A problem with a direct-conversion radio is the presence of DC offset caused by the local oscillator’s self-mixing of a large blocker, thus corrupting the down-converted signal. The solution often requires the baseband to exercise DC-offset correction, usually through the software. In a low-IF receiver, the DC offset is mixed away and filtered out from the desired down-converted signal. Furthermore, low-IF designs usually have integrated synthesizer loop filters and tuning components, preventing reciprocal mixing due to external phase noise sources.

For the transmitter, linear up-conversion architecture is most often adopted for GSM/GPRS, EDGE, CDMA and WCDMA, while polar-loop designs are used mainly for EDGE transceivers today. Linear up-conversion architecture maintains linearity through the transmitter chain, from baseband I and Q signals through the antenna. Radios based on polar loop or polar modulation promise to provide added high-power efficiency, at the expense of the additional calibration and complexity needed to support the power control feedback loop. Furthermore, polar transmitters require a specialized and customized PA to ensure precise matching of the amplitude and phase delays. Unlike polar transmitters, linear transmitters can use widely available PA components.

click the image to enlarge

Figure 4. Single-chip Quad-band CMOS tranceiver block diagram.

Single-chip Quad-band GSM/GPRS Design

To successfully develop a multimode CMOS radio supporting 3G and 2G services, a transceiver IC company must prove its capability to develop and manufacture single-chip multiband CMOS transceivers for GSM/GPRS applications before attempting to design devices with other mode combinations such as EDGE and WCDMA1.

Figure 4 show a design of a quad-band GSM/GPRS CMOS transceiver. The quad-band receiver uses low-IF architecture instead of zero-IF because low-IF tolerates impairments from 1/f noise, DC offsets and finite receiver IIP2 better. The LNAs are implemented as fully differential common-source amplifiers with on-chip inductive degeneration for impedance matching and gain peaking. The LNAs also implement a low-gain mode.

Following the LNAs, quadrature mixers downconvert the desired RF signal to a low IF. The low-IF section of the receiver consists of a fifth-order complex Butterworth filter and PGA. Each complex filter stage contributes to the rejection of the GSM blockers and the image signal and provides programmable amplification of the desired signal. The gain distribution and the sequencing of the filter poles maximize the overall RX SNR. This programmable-gain IF filter, combined with the LNA gain step, incorporates 100 dB of gain programmability. A DCOC circuit prevents IF gain stages from saturating. Resistive cross-coupling between the filter’s I and Q channels cause the DC offsets on the I channel to influence the Q channel, and vice versa. Following the complex filter, a low-IF demodulation circuit downconverts the IF I and Q signals to baseband frequencies using a digitally synthesized clock.

The transmitter architecture is based on an OPLL that includes a quadrature modulator and a fully integrated, low phase-noise RF VCO. Baseband I and Q GMSK signals are frequency translated to an IF by the quadrature modulator. A fifth-order Gm-C low-pass filter eliminates unwanted frequency components. The PFD output is filtered by an on-chip loop filter and is used to drive an RF VCO that covers the GSM-850, GSM-900, DCS-1800 and PCS-1900 bands.

The VCO output drives an on-chip transmit buffer. The RF output level from this buffer is programmable to accommodate different PA modules. Single-ended outputs eliminate the need for external baluns. TX output noise in the receive band (one of the most stringent specifications for a GSM transmitter) is determined by a combination of the on-chip VCO phase noise and the TX pre-PA driver noise. To minimize the noise addition and DC current consumption simultaneously, a rail-to-rail signal swing is preserved from the VCO output to the pre-PA driver input. The transmitter architecture and implementation eliminate the need for all external pre- or post-PA transmit band-pass filters and thus improve transmitter power efficiency.

The time-division duplex nature of GSM is exploited by using a single-frequency synthesizer to generate the local oscillator signals for both the transmitter and receiver. A third-order ΔΣ fractional-N synthesizer is used to provide maximum flexibility for the TX and RX mode frequency plans. A VCO with an on-chip inductor is used to meet both RX and TX phase noise requirements with adequate margin.


Wherever possible, the availability of high-density CMOS logic is exploited by pushing the design complexity into the digital domain. Implementing the best architecture, incorporating extensive DSP techniques and sharing functional blocks are the most essential elements of a successful and cost-effective design.

By first conquering the challenges of implementing single-chip, quad-band GSM/GPRS CMOS transceivers, designers of RF integrated circuits can prepare for the challenging development of single-chip radios supporting EDGE, WCDMA and other wireless technologies. Coupled with highly integrated front-end modules and digital-interface baseband ICs, the resulting CMOS transceiver enables cost-effective and small form-factor multimode handsets.

About the Author

Robert Fan is Vice President of Product Management at Berkäna Wireless. He has Bachelor and Master of Science degrees in electrical engineering and computer science from the University of California, Berkeley and an M.S.E.E. from the University of Santa Clara. Robert can be reached at


1. A Single-Chip Quad-Band GSM/GPRS Transceiver in 0.18µm Standard CMOS" by Rudell et al. at the 2005 IEEE International Solid State Circuits Conference.


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