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Phase-locked Loop

Wed, 06/01/2005 - 7:02am
Semtech announces the ACS8942A, a jitter attenuating and multiplying (JAM) phase-locked loop (PLL) for generating ultra-low jitter output clocks for SONET and SDH network equipment. The IC features jitter generation as low as 0.10 picosecond (ps) RMS (G.813, STM-16, 1 MHz to 20 MHz band) and 0.93 ps RMS (GR-253, OC-48, 12 kHz to 20 MHz band). The device dejitters the output of a line card protection device or line card clock synthesizer, providing a clock-cleaning solution for DSL access multiplexers and metropolitan or edge networking equipment with very tight jitter budgets. With a 5 × 5 mm QFN 32-pin package, the device can be used to attenuate jitter in the network element at the point-of-use. The ACS8942A features an integrated voltage controlled oscillator, which eliminates long-term center frequency drift and the potential for mechanical failure of an external oscillator. The device nominally inputs a 155.52 MHz reference clock via a single, differential LVPECL input and can be configured to provide either 622.08 MHz or 77.76 MHz on a single, differential CML output.
Semtech Corp.
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