3D, Multi-gate Transistor Structures for Next Gen Wireless Devices
By Ernest Worthman, Editorial Director
Glossary of Acronyms
CMOS Complimentary Metal-Oxide Semiconductor
GA General Availability
ITRS International Technology Roadmap for Semiconductors
MOSFET Metal-Oxide Semiconductor Field-Effect Transistors
MuGFET Multi-gate Field-Effect Transistor
NiSi Nickel Silicide
RET Reticle Enhancement Techniques
SOI Silicon on Insulator
SRAM Static Random Access Memory
It's no secret that our thirst for ultrawide bandwidth, feature-rich wireless interconnect devices are taxing the limits of current bi-polar transistor technology.
To that end, the last few years have seen development of transistors with three gates and 3D geometries. Many semiconductor designers on the bleeding edge of development believe that such devices will replace today's devices before this decade's out.
Wireless devices capable of handling TV, voice recognition, or even containing a universal language translator require semiconductor components with densities much higher and footprints much smaller than what is in production today. As well, such features will require these ICs to run much faster than today's devices.
To this end, the semiconductor industry has on its radar screen three-dimensional, multi-gate transistor structures. These 21st century electronic switches are smaller, faster and more tightly packed on ICs than planar, single-gate structures that have dominated the transistor footprint of the past two decades.
All That Glitters Isn't Necessarily Gold
The nagging problem with increasing gate counts, switching speeds and chips that have numbers per chip in the billions is current. Linearly, smaller, more densely packed structures require more current. However, more current causes more heat. The argument can be made that newer designs will require less current per transistor. However, practicality has shown that the proportionality isn't necessarily linear. For example, doubling the gate count usually doesn't inversely reduce the current so both sides of the equation remains balanced. While on-currents may be easier to control it's the leakage currents in the off states that generally increase, causing power consumption to be driven to unacceptable levels.1
Where is the Bleeding Edge?
Since the introduction of these multigate transistors a couple of years ago, today's state-of-the-art is something called a MuGFET. These devices are based on SOI engineered substrates. Furthermore, the latest device has a 45 nm node MuGFET using 248 nm lithography.
Another device on the edge, although several years old, is the FinFET transistor, the latest of which is processed with 193 nm lithography.
MuGFET is a new, non-planar CMOS transistor architecture keeping pace with Moore's Law and the requirements set forth by the ITRS 2003, Emerging Research Devices. MuGFETs are potential candidates to replace planar MOSFETs for specific applications in the 32 nm node due to their excellent control of short channel effects, improved current density and improved gate control compared to conventionally scaled transistors, and, consequently, better intrinsic scalability. MuGFETs are the prime candidates for improving device performance by minimize current leakage when transistors are off. Major semiconductor manufacturers are beginning to examine such innovative transistor structures for designs that are being considered for device technology nodes at 32 nm and shorter. If manufacturability is proven, MuGFETs could eventually replace conventional CMOS transistors. This new technology relies heavily on the use of high quality, very thin SOI wafers as a starting material.
MuGFETS for Memory Density
One of the areas that is in dire need of density improvements is electronic memory. And this area is being studied closely as an emerging market for MuGFET technology. Some work has been done in SRAMs. One notable design is being worked on is from IMEC in Belgium. IMEC's device is a fully working 6-transistor SRAM cell with an area of only 0.314 mm2.
The MuGFETs implemented in the SRAM cell distinguish themselves by a tall fin of 70 nm, 40 nm higher than typically reported so far, resulting in an increased current density. The transistors have a physical gate length of 40 nm and 35 nm wide fins. A NiSi source/drain has been used to lower access resistance and a Cu/low-k (Black Diamond) metallization finishes the cell.
Mature 193 nm lithography with 0.75 NA and RET allowed the patterning of fins, gates and contact holes with 150 nm pitch. The cell layout has been optimized, taking into account the different reticle (phase shift mask) technologies, illumination possibilities (Quasar or Dipole) and optical proximity corrections for each critical layer. Only uni-directional patterns are used, leading to a truly lithography-friendly design.
MuGFETs promise a platform breakthrough in IC density, speed and footprint by offering devices with billions and tens of billions of transistors in a small, low power chip. Prototypes are working but GA is still a few years out (likely near the end of the decade). However, if the demand for broadband heats up, we may see these devices a bit sooner.