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Synthesis/Generator Interface

Mon, 05/02/2005 - 6:04am

Xilinx and AccelChip Inc. announce an interface between AccelChip® DSP Synthesis and Xilinx System Generator for DSP tools which enables development of high performance digital signal processing (DSP) and communications systems. This interface enables designs captured in The MathWorks’ MATLAB® language to be incorporated into System Generator designs for implementation and verification. System Generator for DSP is the framework for developing and debugging high performance DSP systems for Xilinx’s advanced FPGAs. System Generator, together with The MathWorks’ Simulink tool, provides the graphical design environment commonly used by system architects and hardware designers. The AccelChip DSP Synthesis tool and AccelWare® DSP IP cores let algorithm developers synthesize RTL from MATLAB, their preferred language for DSP design. AccelChip’s 2005.1 release extends this hardware design flow with a direct link to System Generator. The interface automatically generates a verified System Generator IP block based on a MATLAB model, enabling cycle-accurate Simulink simulation and hardware synthesis from the System Generator environment.

Xilinx, Inc.

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