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A Practical System Model for the AFE of a Low-IF Receiver

Fri, 02/25/2005 - 7:52am

New single RF mixer, low- or zero-IF output receivers eliminate the need for external SAW filters, thereby lowering system costs and power consumption.

By Bart DeCanne

In recent years, the trend toward on-chip integration of complete RF radio receivers has challenged the hegemony of the superheterodyne radio architecture. IC designers now aim to achieve similar performance by applying single-conversion techniques rather than the superheterodyne's topology of double conversion with channel filtering at a fixed, but relatively high, IF. These new receivers apply a single RF mixer stage, producing either low- or zero-IF output. They implement channel selection on-chip, thereby eliminating the need for external SAW filters. This can result in lower system cost, lower power consumption, and improved manufacturability because of a smaller number of external components.

Hitting Performance Numbers

However, meeting required performance numbers with single-conversion architecture is significantly more complex, if at all possible, because of numerous factors that have traditionally favored Armstrong's superheterodyne receiver architecture. One of the key issues is that in a low-IF receiver, the RF image channel (located at a distance of twice the IF frequency from the desired RF channel) is significantly closer to the desired channel, requiring sharp image reject filtering in an RF pre-select filter or, more likely, requiring the design of a wideband receiver AFE with image rejection and channel selection only performed after RF down-conversion.

Because neighboring channels pass through it, the AFE should be able to cope with the largest possible ILs in all receiver stages prior to the channel filter while still preserving the integrity what may be a weak desired signal. Because the majority of the channel filter is typically implemented in the digital domain — thanks to the possibility of implementing digital filters with zero group delay variation — this architecture poses challenging requirements to the dynamic range of the complete AFE receiver chain as well as to the succeeding ADC.

Furthermore, although the use of CMOS technology for the implementation of the receiver presents advantages in terms of opportunity for integration with digital circuitry and thus lowering overall system cost, CMOS exhibits a larger close-in phase noise of which the power spectral density has a typical 1/f characteristic.

Finally, the lower transconductance of CMOS compared to bipolar or III/V silicon processes and its higher passive component tolerances present additional constraints for designs to ensure robustness over PVT variations.

These are a few of the reasons that commercial implementations of single-chip direct conversion receivers implemented in CMOS have become available only in recent years for systems with challenging performance requirements. For instance, GSM cellular handsets remains an application in which high performance, low power consumption, and high integration are all key.

The Design

The model described in this discussion will attempt to quantify the effects of non-idealities in individual AFE stages on overall performance. During the architectural phase of a receiver design, such a model can be used for first-order dimensioning of individual receiver stages and can give insight as to whether a system specification can be met with the chosen topology.

After introducing the AFE topology, a review of the effects included in the model and the introduction of a suitable metric to quantify AFE performance will be presented. The model is implemented in a spreadsheet showing interactions between these effects on the performance of individual stages and on overall AFE performance. It is shown that the selection of gain settings for individual AFE stages can be treated as an optimization problem, which can be solved numerically in the spreadsheet using the Excel Solver plug-in. Finally, quantitative results for AFE performance are interpreted.1

Receiver Topology

Figure 1 illustrates the analog and mixed-signal components of the receiver. The AFE consists of RF AGC, LNA, RF mixer, PGAs, and ADCs. The RF mixer has a dual output followed by complex processing for image rejection.

Figure 1 Low-IF receiver AFE. Click here to enlarge.

The purpose is to quantify the impact of the following imperfections on overall AFE performance: thermal noise, LO phase noise, and intermodulation. Thermal noise is unavoidable and present in all receiver stages. The effect of a stage's thermal noise on overall performance depends on the stage voltage gain, I/O impedance matching between succeeding stages, and other fixed external parameters such as signal bandwidth. LO phase noise impacts performance through the effect of reciprocal mixing, as shown in Figure 2. Its effect is greater when neighboring channels or interferers are close to the desired RF channel, when there are more interferers, and with larger channel bandwidth. For intermodulation distortion, only IP3 effects are quantified because in a practical receiver, IP3 is likely to be the dominant effect compared with IP2 intermodulation, which can be reduced by using differential design. IP3 will deteriorate performance most when two interferers are present at frequencies f1 and f2 such that the component at frequency (2 3 f1 - f2) forms an in-band signal that cannot be eliminated by the channel selection filter. The model is limited to two interferers. An extension to additional interferers is straightforward and may be needed for some systems.

Figure 2. Reciprical mixing of LO phase noise with interferer and spur components. Click here to enlarge.

The receiver is designed to minimize the total AFE performance degradation caused by these effects applied to individual receiver stages and their individual effects appropriately cascaded for the impact on overall AFE performance. DR is a suitable performance metric for the AFE. For our purposes, DR is defined as the difference in decibels between the maximum RMS input level (the RMS sum of desired and all interferer components) and the receiver SL.

Sensitivity Level, Interferer and SNR Issues

The SL is the desired input signal of lowest amplitude for which the receiver can generate an output of "sufficient quality." Thus, the receiver noise floor should not be higher than SL - SNR(min), with SNR(min) equal to the minimum required SNR for the given modulation and channel coding system. SNR(min) is system-dependent and can be as low as a few decibels for a QPSK-modulated digital satellite television receiver or may need to be a few tens of decibels for analog systems such as AM radio and analog NTSC terrestrial video. When the channel filter is fully implemented in the digital section of the receiver, the sum of AFE DR and SNR(min) also presents a minimum SNR requirement for the ADC that follows the receiver AFE. However, by incorporating some channel selectivity within the AFE, the dynamic range requirement on the ADC (as well as selectivity requirements of the digital channel selection filter) can be lowered. The DR concept can also help in trading off analog vs. digital performance requirements of the receiver.

Figure 3 represents DR vs. IL, referenced in decibels vs. SL level, as a linear curve, up to the point where one or more of the AFE effects listed starts to significantly degrade performance. Depending on the severity of the relative effects, the receiver's DR can become either noise-limited (because of thermal or phase noise) or distortion-limited (IP3).

Figure 4a. Cascaded IP3 calculation with equal interferer levels.Click here to enlarge.
Figure 4b. IP3 calculation with unequal interferer levels.Click here to enlarge.

At ILs where the curve starts to flatten, the receiver is said to desensitize. For example, the AFE dynamic range is insufficient to pass a weak desired signal at SL and the high ILs without causing overload/clipping of the input signal. Assuming the AGC attenuates to avoid overload, the receiver's real SL in the presence of these interferers will have deteriorated by an amount equal to the distance between the linear 1:1 curve and the actual DR for a given IL. Receiver desensitization, because of this lack of dynamic range in the AFE, cannot be recovered by post-processing in the digital part of the receiver.


Conceptually, the receiver AFE model can be treated as a black box defined by a set of externally imposed performance requirements, a set of internal performance parameters that are obtained from simulation of individual receiver components (design constants), a performance metric that should be optimized (optimization criterion), and a number of "knobs" to tweak to achieve best performance during operation (optimization variables). Table 1 gives an overview of these parameters.

An optimum gain setting for each stage within the "design constraints" of allowable gain settings should be determined from minimum/maximum gain and gain increment inputs for each stage such that the overall AFE dynamic range is maximized for a given set of interferer frequencies and levels.

Modeling Individual Receiver Stages

The RF AGC is modeled as a resistive divider. When the total input signal consisting of desired and interferer levels becomes too high, a voltage divider attenuates desired and undesired components by equal amounts when there is no antenna tuning circuit in front of the RF AGC. The LNA, mixer, and APGA can also have a variable gain. Because it lowers the signal in all AFE stages, one would expect the RFAGC to start attenuating the input signal as a last resort and, thus, only at extremely high interferer amplitudes when the gain settings of other stages are already at their minimum. However, this is not necessarily the AGC strategy that yields maximum overall DR.

A separate LNA amplifies the input signal to the RF mixer. Next to having a thermal noise specification, LNA, mixer, APGA, and ADC are also characterized by an IIP3 number. IIP3 numbers are design constants (e.g., retrieved from transistor-level simulations). Because higher gain settings can correspond to significantly lower IIP3, especially for the RF mixer, it may be more accurate to enter a table of IIP3 vs. gain values for individual stages so that the model will adapt its IIP3 calculation depending on the selected gain. Note that we use a stage-IIP3 number (e.g., the IP3 referred to the input of the stage itself). The model calculates the cascaded total AFE IP3 number from these individual stage contributions taking into account stage gains, I/O impedances and the frequency-selective attenuation of both interferers in each stage. This is an important caveat: The textbook formula for cascaded IP3 shown in Figure 4a is only valid when both interferers are of the same amplitude throughout the receive chain.

This is not the case when individual receiver stages are frequency-selective. In that case, both interferers at f1 and f2 have unequal amplitudes at various points in the receive chain (e.g., A1 and A2). Figure 4b shows how to calculate the amplitude of the resulting IP3 component in this case. The formulas in Figure 4b assume power and IP3 numbers are expressed in a logarithmic unit.

At high IM3 levels, resulting from high ILs and/or low stage-IIP3 numbers, the receiver will become "distortion"-limited. The IM3 component (at frequency f0) should be added in the RMS sense to the desired RMS voltage component at f0, and the total signal propagating through the receiver AFE is the sum of this component at f0 and both interferers at f1 and f2.

On one hand, it is desirable for the receiver to use high gain settings to minimize DR degradation due to thermal noise — the DR limitation due to thermal noise is noted as DR(TN). On the other hand, lower gain settings reduce IP3 distortion and are needed at high input levels to avoid overload on any input stage. DR degradation due to LO phase noise via reciprocal mixing is noted as DR(PN) and total DR as DR(TN+PN+IP3). To maximize total DR, the stage gain settings can be treated as the independent variables of an optimization problem with optimization criterion: maximum DR. The model contains expressions for total input amplitude at the input of each AFE stage, consisting of desired and interferer signal as well as noise and IP3 contributions. These expressions are bounded by the overload level and thus inequalities. Various trade-offs can be run by inputting different values for the design constants of Table 1. Alternatively, a more advanced model could try to include these as optimization variables.

Results of Receiver Optimization

It is now possible to interpret some quantitative results obtained with this low-IF receiver model for a receiver AFE operating at an RF input frequency of 100 MHz (= f0) with a 200 kHz RF channel bandwidth and using a low-IF in the few hundred kilohertz range. We use the Excel Solver function to determine the "optimum" stage gain settings for two (equal) ILs at successively SL+20, SL+30, up to: SL+110 dB. Assuming SL at 0 dBµV, we can express ILs in dBµV. The interferers are modeled at frequencies f1 = 100.4 MHz and f2 = 100.8 MHz; thus the IM3 product at (2 3 f1 - f2) lands on top of the desired channel.

The DR vs. interferer amplitude curve (each point on the plot is a result of our optimization and thus the best DR achievable for the corresponding ILs) and the corresponding gain settings for each receiver stage are shown in Figures 5a and 5b. Next to overall DR, DR(TN) and DR(PN) subcomponents are also shown.

Figure 5a. DR vs. IL for two interferers. Click here to enlarge.
Figure 5b.Gain vs. IL for two interferers. Click here to enlarge.

When only a single interferer is included, which excludes IP3 effects, and all other receiver parameters are kept identical, the results of Figures 6a and 6b are achieved. In the single interferer case (Figure 6a), the DR is significantly higher at the same IL. It can be concluded that this receiver is distortion-limited rather than noise-limited. This is confirmed by the gain plot in the dual-interferer case (Figure 5b): the RFAGC starts attenuating from a IL of about 60 dB before other stage gain settings are reduced. The AFE reduces the signal level in the receiver to combat IP3. Indeed, since IP3 increases at a 3:1 ratio versus the input signal amplitude, the resulting degradation dominates the 1:1 sensitivity loss because of the action of the RFAGC in the case of a distortion-limited receiver.

Figure 6a. DR vs. IL for 1 interferer.
Click here to enlarge.
Figure 6b.Gain vs. IL for 1 interferer.
Click here to enlarge.

Because the RFAGC compensates for higher ILs by using additional attenuation, a flat DR plot results, up to the point when the RFAGC maximum attenuation limit is reached. Then other stage gain settings must be lowered, which has a detrimental effect on DR and thus receiver desensitization.



Table 1. Parameters for the Low-IF Receiver Model
Receiver specifications
Input sensitivity level µ V]
RF frequency of desired channel (F0) [Hz]
RF channel bandwidth [Hz]
Operating conditions
RF frequency of interferer #1 (F1) [Hz]
RF frequency of interferer #2 (F2)[Hz]
Input (interferer) level(s) @(F1) & (F2)[dB µ V]
Design constants
Stage input resistance [Ω]
Stage output resistance [Ω]
IF frequency [Hz]
Stage minimum & maximum voltage gain and gain increment [dB]
Stage full-scale input voltage [Vrms]
Stage input noise voltage density (i.e., thermal noise) [Vrm/sqrt(Hz)]
Stage IIP3’s at all possible gain settings [dBµV]
LO phase noise at a given distance from LO frequency [dBc/Hz]
Stage headroom level [-dBFS]
Stage attenuation vs. frequency characteristic [dB]
Optimization criterion
Maximum dynamic range [dB]
Optimization variables
Stage voltage gains at given signal and interferer levels and frequencies (i.e., the "AGC strategy") [dB]

At first glance, DR(TN) also appears to be a limiting factor; however, this is only a consequence of the RFAGC limiting signal input amplitude to combat IP3 and thus increases the effect of thermal noise. This is clear from the single-interferer case: DR is as much as 10 dB higher and is limited by DR(PN) and DR(TN). As seen in Figure 6a, with rising IL, the APGA starts attenuating the signal first, followed by LNA and RFAGC, as we would expect in a noise-limited receiver. Although the overall total gain is always monotonically decreasing with increasing IL as would be expected (the particular shape is affected by the entered gain step sizes and ranges), Figure 6b shows that the LNA gain can actually increase again at some point once the RFAGC kicks in. Finally, DR(PN) in a dual-interferer scenario is lower than for the single-interferer case because with two interferers, there is an additional contributor to reciprocal mixing.


A receiver model such as the one developed in this discussion can provide a first-order dimensioning of a receiver AFE and helps one to gain insight as to whether a chosen receiver topology will reach required performance specifications. With limited input from transistor-level simulations, the system engineer can quantify the effect of various imperfections on AFE performance and make trade-offs between the target performance of individual AFE stages. The dynamic range concept discussed also helps in partitioning the design between the analog and digital sections of a receiver.


1. It should be noted that for proprietary reasons, the results shown in this article are hypothetical and do not reflect performance numbers of any commercial product. Only a simplified version of the model is presented in this article for tutorial purposes.

About the Author

Bart DeCanne joined Silicon Laboratories, Austin, TX, as product marketing manager in 2004. Prior to joining Silicon Laboratories, DeCanne held a marketing manager position at Barcelona Design. He also was a strategic marketing manager at Texas Instruments and a hardware engineer for Barco Broadcast and Cable in Belgium, currently a division of Scientific-Atlanta. DeCanne has a master's degree in electrical engineering from the University of Ghent in Belgium and a master's degree in business administration from the University of Texas at Austin.

Glossary of Acronyms

ADC - Analog-to-Digital Converter
AFE - Analog Front End
AGC - Automatic Gain Control
AM - Amplitude Modulation
APGA - Analog Programmable Gain Amplifier
CMOS - Complementary Metal-Oxide Semiconductor
DR - Dynamic Range
GSM - Global System for Mobile Communications
IC - Integrated Circuit
IF - Intermediate Frequency
IIP3 - Input Third-Order Intercept Point
IL - Interferer Level
IM - Intermodulation
IP2 - Second-Order Intercept Point
IP3 - Third-Order Intercept Point
LNA - Low Noise Amplifier
LO - Local Oscillator
NTSC - National Television System Committee NTSC refers to the analog TV standard used in North America and parts of Asia (Korea, Taiwan, Japan)
PGA - Programmable Gain Amplifier
PVT - Process/Voltage/Temperature
QPSK - Quadrature Phase-Shift Keying
RF - Radio Frequency
RMS - Root Mean Square
SAW - Surface Acoustic Wave
SL- Sensitivity Level
SNR- Signal-to-Noise Ratio Thermal Noise


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