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Mismatch Models

Wed, 09/29/2004 - 8:11am

PolarFab introduces Monte Carlo mismatch models that improve design support for the company's PBC4 BCD/BiCMOS process. The models optimize analog and mixed-signal integrated circuit performance and create shorter design cycles. Monte Carlo mismatch models enable the simulation of mismatch behaviors for all major PBC4 devices such as resistors, capacitors, 5V CMOS, and bipolar transistors. The models optimize circuit designs by allowing designers to center the design for optimum manufacturing yield, improving product performance, design robustness, and product quality. The result is shorter design cycles as well as a lower cost per die, since designers no longer need to over-design circuits. The PBC4 process, available on 6 inches and 8 inches wafers, features 0.5 micron, 40 V BCD/Power BiCMOS technology. The process includes complementary N- and P-channel MOSFETs with 5, 7, 16, and 30 capabilities as well as a 40 V capability for NMOS only; dual gate oxides (5.5 & 16 V); a 16 V poly-poly capacitor, a ZTC poly resistor, two high-value diffused resistors, a Schottky diode, a lateral PNP and two vertical NPN transistors. Two- and three-layer metal versions of the process are also available.

PolarFab

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