National Semiconductor Corporation debuts a new dual high-performance CMOS analogue-to-digital converter that consumes significantly less power while providing the gigahertz speeds necessary for reliable measurements of high-frequency signals. These high-speed, low-power devices are designed specifically for applications such as digital oscilloscopes, automated test equipment (ATE), base stations, satellites, and communications systems requiring direct I/Q down-conversion. As one of the key building blocks in system signal path designs, ADCs accurately capture real-world analogue information and convert it for processing in the digital domain.

These high-speed, low-power devices are designed specifically for applications such as digital oscilloscopes, automated test equipment (ATE), base stations, satellites, and communications systems requiring direct I/Q down-conversion.

High Speed Conversion, Low Power Consumption

The ADC08D1000 digitizes two input signals to 8-bit resolution at sampling rates up to 1 Gs/s while consuming 1.6 watts from a 1.9 V nominal supply. By using the fully programmable dual-edge sampling feature, the product can achieve 2 Gs/s sampling from one channel by interleaving the two on-chip converters. Both coarse and fine timing adjustments are available, allowing the sampling clock for each channel to be calibrated independently in 0.1 ps increments. A three-wire serial bus controls these adjustments, as well as on-chip functionality, and independent gain and offset fine-tuning for I and Q channels. The ultra-low power requirements of the ADC08D1000 enable designers to eliminate fans or heat sinks, saving board space and reducing system cost.

Performance Enhancements

The device is fabricated on 0.18-m high-performance CMOS process technology. The chip features on-chip auto calibration at power-up that enables low power with high performance. In addition, it offers performance-enhancing folding/interpolating architecture. Folding reduces the number of comparators, and interpolation greatly reduces the number of front-end amplifiers required, saving power and reducing the load on the input signal. The ADC08D1000 has an ideal pulse response and guarantees "no missing codes" over the full operating temperature range of – 40° C to +85° C. In addition, it features a LVDS interface that enables reliable transmission of high-speed signals, while maintaining low noise and distortion levels.
The ADC08D1000 is designed with a BER of 10-18. At a 1 GHz sampling rate it achieves 0.25 LSB DNL, 0.35 LSB INL and maintains 7.5 ENOB from DC up to a 500 MHz input (Nyquist). Measured crosstalk between the I and Q channels is less than – 77 dB. The dual on-chip sample-and-hold amplifiers deliver dynamic performance over a 1.7 GHz full power bandwidth.
Following soon will be a 500 Ms/s version and National's 1.5 Gs/s device in the first quarter of 2005. All speed grades in this ultra-high-speed portfolio have the same pin-out, allowing the designer to change the sampling rate without changing the board layout. In addition, National is developing higher-resolution 14- and 16-bit pipeline ADCs and continuing to build its low-power, general purpose SAR (successive approximation register) ADCs for broad market applications.
The ADC08D1000, housed in a 128-lead exposed-pad package, is priced at $219 in 1K volumes. The product is scheduled for full production release in January 2005 and samples will be available at that time.
National Semiconductor Corporation