Indium Phosphide is maturing as a mainstream technology for both electronic and optical functions.By Minh Le
Indium Phosphide has compelling properties that make it a useful material for both electronic and optical functions. It is a direct bandgap semiconductor whose energy gap allows the generation and detection of light at 1.3 to 1.55 μm spectral range, wavelengths that exhibit minimal loss in glass fibers for optical communications. Other material properties of InP, such as higher electron mobility (~9 times that of SiGe and 2 times that of GaAs) and higher breakdown voltage (~2 times that of SiGe), make it suited for high speed and high breakdown voltage electronic applications. Table 1 summarizes the material properties of InP in comparison to GaAs and silicon. These and other excellent electrical properties of Indium Phosphide Heterojunction Bipolar Transistors make them ideally suited for the particular demands of high frequency RF and mixed signal circuits.
Figure 1. A new method of manufacturing InP HBT devices involves the extensive use of dielectric spacers to define critical dimensions. This technique allows for creation of feature sizes and separations that has much tighter control than reliance on just optical lithography would.
Si, GaAs, and InP
The compound semiconductor industry has too long rested on the material property advantages over silicon alone. Though electrons in silicon do not travel nearly as fast as in some compound semiconductors such as GaAs or InP, the most advanced CMOS of SiGe bipolar processes make sure that they do not need to travel very far. Transistor gate length has been scaled dramatically over the past many decades, with CMOS effective gate lengths on the order of 100 nm.
Shrinking the transistor has brought about speed improvements. In the silicon industry, the shrinking was also done with the requirement of yielding a hundred million transistor circuits, a requirement that dictates that only high yield manufacturing processes are employed. In the quest for ever faster and faster transistors, compound semiconductor development has relied on manufacturing practices such as lift-off contact metallization, T-gates, and e-beam lithography. These techniques have long been abandoned in mainstream silicon processing and can significantly limit yield of complex circuits.
For example, lift-off is a particle generating process that has a tendency of creating electrical shorts. Though perhaps not a dramatic yield limiter for MMIC circuits that have only tens of transistors, yield statistics become untenable when the transistor count is increased to tens of thousands. A HBT process designed for high-transistor count and very high speed mixed signal circuit applications processed on 4-inch diameter InP wafers. The emerging mixed signal IC market segment for end applications that include radar signal processing requires a technology which can support several thousand to tens of thousands of active devices in a single circuit with acceptable yield, and produce ICs which operate at clock rates in the range 50-100GHz. Adopting silicon industry standard processing techniques and device structures provides a straightforward means to achieve these goals.
HBTs Step up to the Plate
A representative diagram of an HBT is shown in Figure 1. Before device processing, the different layers of the HBT are grown by MBE. Carriers generally move vertically through the transistor, and are transported by the built-in and externally applied electric fields. A figure of merit of the transistor, Ft or the cut-off frequency, is dominated by the transit time of carriers through the base and the collector (see Formula 1).
This is highly dependent of the epistructure of the HBT and the layer thicknesses. Carrier transport through the base can be greatly enhanced through bandgap engineering. A compositionally graded base (wider bandgap InGaAsP at the emitter-base junction to InGaAs at the base-collector), applies a built-in electric field to the carriers such that they accelerate through the thin base instead of relying the much slower diffusion process. Ft does not significantly depend of the lateral dimensions of a transistor, just the epilayer thickness and bandgap properties of the device.
Another figure of merit for transistors is Fmax, the maximum oscillation frequency. Fmax is a function of Ft and the base-collector RC charging time and is strongly impacted by the device geometry, both vertical and horizontal dimensions. To have high Ft, we simply want to thin the base and collector, but this has the adverse impact of increasing the base resistance Rb, and the base-collector capacitance, Cjc that in combination will lower Fmax. A compromise must be met to attain near parity between Ft and Fmax.
The second generation of this process optimizes the speed of the transistor by scaling both the vertical and horizontal dimensions. Compared to the earlier process, the collector thickness is reduced from 300 nm to 150 nm. By doing so, Ft is more than doubled from 150 GHz to over 300 GHz. Shrinking the emitter width from 1.2 mm to 0.35 mm and using self-aligned spacers to determine critical feature sizes and separations improved Fmax from 150 GHz to over 300 GHz. It is a technique that borrows heavily from silicon CMOS processing where dielectric spacers separate the gate from the source and drain regions.
Figure 4. Spectrum analyzer output of a static divide by 2 circuit fabricated on the VIP-2 process. The above results demonstrate 152 GHz operation.
In this new HBT process, the dielectric spacer is used to separate the emitter and base terminals of the transistor. The use of dielectric spacers instead of optical lithography allows definition of fine feature geometries with much more accuracy and control because overlay margin between masking layers is eliminated. Features smaller than the optical stepper resolution limits can also be created through the use of spacers.
Furthermore, it is possible to minimize the RC charging time by precisely controlling the base metal width. The base metal is deposited and etched instead of using lift-off contact metallization, which as discussed before can limit yield in high transistor count circuits. Figure 2 demonstrates how there is an optimal base metal size.
As the base metal is made wider, the contact resistance is reduced because there is more base metal to semiconductor contact area. However, Cjc is increased because the parallel plate capacitor between the base and collector has increased in area. At an intermediate width related to the transfer length of the base contact, there is a minimum in the RC charging time, and hence an optimal Fmax. This is accomplished while keeping the breakdown voltage BVceo at more than 4.5 VDC, more than twice that of high-speed SiGe devices.
Along with the very high speed transistors, a metal interconnect system must be available to route 100 GHz speed signals around the circuit. Interconnects become just as important as the transistor itself at this high frequency. It is here that the compound semiconductor industry has lagged the silicon industry significantly.
Whereas seven to eight levels of copper interconnects may be common with CMOS processing, 2 levels of air-bridged gold interconnect structures may be more typical with III-V processes. Furthermore, since thermally stable ohmic contact metals were chosen for the transistor and tested to over 400° C, the interlevel dielectric material can be PECVD oxides, a common ILD material in silicon processing versus polyimide or BCB that is often used with typical III-V processes. With the needs of mixed signal circuits that may demand tens of thousands of interconnected transistors in mind, the VIP-2 process was developed with four levels of interconnect metal along with an extra local interconnect routing layer.