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Designing for Secure Digital I/O

Mon, 08/30/2004 - 7:47am

Today's system designers are faced with many possible I/O functions that can be included in their design. These range from wireless options such as WLAN, Bluetooth or wideband technologies, to data collection options such as Barcode scanning or RFID readers.

One way to manage the many options is to build in a plug or slot that can take many different I/O functions using existing standards to allow the system designer to take advantage of a wider variety of I/O peripherals.

Secure Digital I/O card

Secure Digital (SD) is ideally suited for handheld devices in many ways, the most obvious due to its small size, 1.4 mm x 24 mm x 32 mm, only slightly bigger than a postage stamp.

A well designed handheld device will have allowances for SDIO cards that can be extended; such as placing the SDIO slot at or near the top of the handheld and no permanent cover over the slot.

Another important criteria for any plug in technology is the cost of the slot. One way that SD/SDIO keeps the cost of the slot down is by only requiring a small number of connector pins. SD/SDIO cards are built with nine connectors on the card, which support three different bus modes: seven-pin serial interface (SPI), 1-bit SD and 4-bit SD. SPI and 1- bit SD modes require only six active connections, including power and ground. SD 4-Bit mode adds three more data lines for four times the performance; however, not all SDIO cards support 4-bit mode, but most SDIO Host controller chips do support it, so the cost is almost negligible.

Multiple slots can be supported either in a bus topology or in a star topology. Most multi-slot systems will use a star topology, as bus topologies are subject to electrical issues when hot swapping, extra overhead for selecting the appropriate card, and are forced to the lowest common denominator regarding performance issues, such as clock speeds, bus widths and voltage selection.

SPI mode is the simplest mode of operation supported by SD/SDIO and can be implemented completely in software for a very low cost; however, the performance will be low. Most designs will utilize an existing SPI controller included in the host processor for the low level SPI and only do the protocol portion of the SD SPI interface in software. This can allow for a theoretical transfer rate of 20 Mb per second if the maximum clock rate of 20 MHz is used. Systems requiring higher performance and robustness should use the preferred SD1/4-bit interface with a 25 MHz clock rate, allowing for theoretical through put of 100 Mb per second (25 Mb in 1-bit mode). Both SPI and SD modes require cyclic redundancy code (CRC) checking on all data, but SD mode adds more error retry capabilities.

Many current processors include a full SD Host Controller built into the chip, including many variants of the Intel XScale. Adding an appropriate connector is all that is required for these processors to add hardware support for SD Memory and I/O cards.

The major hardware requirement for a slot that supports SD memory for SDIO is interrupt handling. An SPI or 1-bit slot supports interrupts by monitoring one of the otherwise unused 4-bit data lines. This can generally be done with any general purpose I/O (GPIO) input on the host processor. A 4-bit implementation must look at the Data 1 line either when the bus is idle (not transferring data) or between data blocks.

Every SDIO card contains up to eight logical sections: Function 0 is the common SDIO control section, and Functions 1 to 7 are the actual IO functions. An SDIO card must be designed to utilize Function 0 and Function 1. Functions 2 to 7 are optional. Each Function, including Function 0, must have a Card Information Structure (CIS). The CIS is defined by the Personal Computer Memory Card International Association (PCMCIA) and includes information on the voltage and power requirements of each Function, its functionality information about the manufacturer, including an ID number assigned to the manufacturer by the PCMCIA or the Japan Electronic Industry Development Association (JEIDA). Additionally, each Function has a set of registers that provide additional information about the card and the Functions on the card, including a pointer to the CIS information. These registers include specific SD bus information for the card, such as clock speeds supported, bus widths supported (1-bit or 4-bit), interrupt control and Function enable bits.

A major component of an SD/SDIO implementation is the software to drive the bus, commonly referred to as the Bus Controller Software. The bus controller software handles the low level bus initialization, basic data transfer, card detection and initialization and, most importantly, determining the correct card function driver to load. For an SDIO bus, there are two ways the correct function driver can be determined. 1) If the card Function is one of the defined application Functions, which at this time are Bluetooth (two types), Personal Handy Phone Systems (PHS), Global Positioning Systems (GPS) and Camera. For each of these Function types register mappings and protocols have been defined to allow a standard driver to be written. 2) If the card function does not fit into one of these categories, the card's CIS can be used to generate a unique Plug and Play ID. There is no standard method for generating a unique Plug and Play ID, each operating system (or bus driver) is free to calculate an ID as required. Usually, the CIS data is used to generate a unique CRC value. Since the CIS information includes vendor and product IDs and function types, this works quite well.

The SD/SDIO bus is essentially a serial interface, with 4-bit mode providing some optimization. Additionally, all transactions over the SD/SDIO bus are done in a command/response format. An SDIO command to read or write a single byte, such as a status register, consists of 48 bits and a response of 48 bits, both including the data. Thus, there is a significant overhead for doing single byte transactions. SDIO products that have low data rates, such as GPS receivers and Barcode scanners, have mapped a 16550 Universal asynchronous receiver/transmitter (UART) onto the SDIO bus, necessitating many single byte read and write operations. However, at the low data rates these devices communicate at, this is not a problem. Devices requiring higher data rates, such as Bluetooth receivers and Wireless LAN cards, have been optimized such that large packets can be sent and received, thus minimizing the command/response overhead and taking advantage of the block oriented nature of the SD/SDIO interface.

By Leonard Ott, Chief Technical Officer, Socket Communications


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