Compact LTCC Package Modeling Techniques
By Ted A. Miracco, Lloyd Nakamura, and Malcolm Edwards
LTCC design poses challenges because it required flexibility in simulation, three dimensional layout, and integration. A highly integrated EDA solution with openness to customization for LTCC components design methology, addresses this issue.
LTCC modules are emerging as an important solution for wireless applications based on competitive advantages in size, cost, and time-to-market1. Despite the many advantages, LTCC development is undermined by a variety of unique technical challenges that limit the impact of EDA solutions. Traditional EDA tools have typically been "hard wired" to address either PCB design or IC design, neither of which provides all the essential features or functionality to be effective in designing LTCCs.
Although LTCCs combine some of the characteristics of both dense PCBs and ICs, effective simulation requires capabilities that go beyond the standard design methodologies for either of these applications. Deficiencies in typical EDA solutions for RF module design can generally be classified into three categories: simulation issues, layout issues, and integration issues.
Understanding LTCC Requirements
The critical requirement for effective LTCC development is an EDA solution that combines the essential simulation technologies with comprehensive and flexible layout capabilities. Some of the issues today that undermine LTCC development are insufficient or inefficient abilities to model the interconnect and associated parasitics related to dense module development.
Although some frequency-domain and time-domain (SPICE) simulators include transmission line and even coupled transmission line models, the geometric complexity of LTCC layouts ultimately requires planar 3D EM simulation in addition to standard models or parasitic extraction methods. It is ideal to have access to multi-level modeling approaches2, as indicated in Figure 1, such that the user can make trade-offs in simulation accuracy vs. the computational efficiency as the design progresses from concept to final mask generation. EM analysis is not only essential to the final validation of a design, but ideally can be combined with circuit simulation to provide an interactive design methodology that supports real-time tuning and optimization.
Figure 1. Ideally, an EDA solution should provide multiple levels of abstraction for transmission lines, such that engineers can trade off accuracy and computational efficiency.
In addition, the EDA tools should address the statistical variations and process corners that occur in volume manufacturing of LTCCs. A best-case scenario can provide multiple EM solvers that are all integrated with general purpose circuit simulators to eliminate the possibility of error in importing simulation data, and provide a mechanism for easily comparing results from a variety of solvers.
To demonstrate the design process a simple passive discontiguous narrowband GSM/DCS diplexer circuit will be used. The LTCC design methodology will be built using a design environment and simulation tools from Applied Wave Research and will leverage interfaces to third-party EM simulation tools, including NetAN, a parasitic extractor from OEA International, Inc., and em, a planar EM simulator from Sonnet Software.
Developing an LTCC Process Design Kit
The first step in establishing an LTCC design methodology is the development of a PDK. PDK development involves building a custom library of electro-physical models supported by the specific process. In addition to process-specific models, a customized layers file (LPF) must be created based upon the specific dielectric and metallization layers chosen for the design. The layers file will be utilized by both the simulation and layout tools to synchronize the placement of components within the dielectric stack up, and provides for the ability to easily cut and paste layout geometries into a/an EM simulator(s) for final verification.
One of the many advantages of an LTCC is the ability to create highly compact designs by leveraging the large number of layers at the engineer's disposal. In this case a 14-layer LTCC structure will be selected, as it will allow sufficient vertical separation to isolate the two filter sections using a ground plane. By effectively isolating the filter sections, the extraneous coupling between components and the need for computationally expensive full wave 3D EM analysis can be minimized.
User-defined EM-based Models/Cells
In order to take full advantage of the LTCC process, it is essential to develop a set of custom models for structures that go beyond the standard microstrip, stripline, and coplanar waveguide elements in most standard RF EDA solutions. In the case of the GSM/DCS diplexer, compact inductive and capacitive elements that maximize the opportunity of utilizing the Z-plane will be required. While it would be possible to create the two-layer rectangular microstrip inductors that are popular inMMICs, it is far more cost- effective to build the inductor on successive vertical layers in an LTCC process, as seen in Figure 2.
Figure 2. Compact vertical inductors reduce size and cost of LTCC components.
The challenge in doing so, of course, is that while many years of research, tests, and measurements have been applied to modeling planar flat GaAs spiral inductors, each LTCC process is unique and foundries must invest in characterization of the vertical spiral structures for engineers to take advantage of the process. In most cases LTCC foundries have utilized either 3D EM simulators or measurements to generate fixed artwork cells that are tied to S-parameter data. However, in the case of the narrowband diplexer, it is highly desirable to have access to accurate, continuously scalable parametric models such that the performance can be tuned or optimized for the frequencies of interest.
Creating the vertical spiral model is accomplished by first running the software model wizard application, which will automatically generate C++ code based upon a set parameters and a topology specified by the user in the form of a netlist. The resulting compiled model is programmed to leverage a built-in 2D quasi-static EM cross-sectional solver3, which will account for the coupling between all the parallel segments of the spiral. Upon compilation, the user needs to place an independent DLL element into a model's directory to gain access to this new element. The key difference between the results is in simulation time. The circuit-based model solves in a few seconds while the full wave EM simulation takes approximately 10 minutes for a comparable number of frequency points. Both representations provide consistent results, as shown in Figure 3.
Figure 3. Validation of the vertical inductor model where the circuit-based model is compared from DC to 10GHz against a full wave EM simulation using EMSight solver.
Another element required for the diplexer is a multilayer parallel plate capacitor. The electrical representation, depicted in Figure 4a is implemented as a parametric sub-network containing transmission lines and capacitors from the standard element catalog. The corresponding parametric layout cell generator is created using a C++ routine that is compiled and loaded into the program with the user-defined models.
Figure 4a. A multilayer capacitor can be electrically modeled using a series of standard elements, including quasi-static transmission line and coupled transmission line models.
Figure 4b. A corresponding compiled parametric layout cell is used to generate the physical representation.
This compiled model library has many advantages for the LTCC foundry and designers, including performance, accuracy, distribution, and protection of IP. In terms of performance, a compiled model will execute more efficiently than an interpreted version of the same model. In addition, because the model is based on EM first principles, it should be more accurate and have greater dynamic range than closed-form equations, which are usually based upon a limited data set.
An additional benefit of compiled DLLs is distribution, as the files are small enough to be distributed as an email attachment and can easily be updated if there are process changes or new models. Lastly, compiled models protect the IP of the model developer since other parties cannot easily decompile the underlying code.
Implementing the Diplexer Design in LTCC
Once the basic building blocks for the design are in place, it is straightforward to move from concept to implementation. The basic element values are determined using a filter wizard to establish ideal values for the inductors and capacitors of the two filter networks. Because the diplexer is discontiguous, it is not necessary to be overly concerned with the impedances at the junction of the two filters, provided the connections to the first resonator are electrically small. The only decision is determining how many filter sections are required to meet the 㪬 dBm isolation requirements for the diplexer. And, because some degradation of the design from stray coupling and manufacturing variations can be expected, it is prudent to add additional filter sections to provide a sufficient margin for implementation.
From this point the diplexer is constructed by connecting the ideal filters and analyzing the structure with a linear circuit simulator to determine if it meets all the specifications. Next, the ideal inductors and capacitors are replaced with the LTCC elements (see Figure 5), and the parameters are adjusted to match the ideal values from the synthesized networks.
Figure 5. Layout implementation of a GSM filter section using LTCC components.
Circuit simulation of the LTCC implemented design typically results in some disparity from the ideal model (see Figure 6). At this point it is possible to either tune on the element values to restore the correlation of the two structures, or use the optimizer to accomplish the same goal.
Discrete Value Optimization for EM Analysis
Figure 6. Physical implementation of the LTCC filters results in degradation of transmission and rejection characteristics.
Full wave EM simulators are required to take into account all of the extraneous coupling between the interconnect and the LTCC cells. Although full wave MoM simulators are available in both gridded and non-gridded formulations, it has been determined that the gridded methods have greater accuracy and dynamic range vs. the more geometrically flexible non-gridded approaches5. However, optimizers are typically geared to continuous functions. This can result in values that force the user to compromise between either long simulation times that result from a fine grid or inaccurate results stemming from descritization error due to non-conformance of the structure with the EM grid. This problem can be mitigated or eliminated, completely, by utilizing a discrete value optimization algorithm that will adjust the structure in specific increments that correlate with the selected grid of the EM simulator. Use of this technique significantly reduces the design cycle by cutting the time/EM iteration, while dramatically increasing overall confidence in the design process.
Space Mapping and Decomposition
It is also possible to combine circuit simulation in concert with EM simulation to rapidly assemble the building blocks of the diplexer through a technique called space mapping and decomposition6. This approach uses the EM simulation sparingly as a means to calibrate a computationally more efficient circuit-based simulation.
Applying this approach to the filter designs is best accomplished by breaking the filter designs into physically isolated components and comparing the resulting S-parameters from EM simulations to the circuit-based approach. Next, the delta between the two sets of S-parameters is taken and cascaded with the circuit simulation results to re-calibrate them to match the EM results. This new circuit-based network provides an accurate and efficient means to re-optimize the design for final assembly.
Final Validation Using EM Socket
With the emergence of open computing standards, such as Microsoft's Component Object Model, it is possible to tightly and seamlessly integrate simulators from multiple vendors within a common design environment. Software now includes a COM-based EM Socket interface that acts as a server such that structures can be simulated with third-party solvers in addition to the native EM-solver.
This provides a mechanism for engineers to validate results with multiple EM solvers. In the case of the diplexer structure, electrically small sections of the filters were analyzed using the EMSight MoM.
Figure 7. Electromagnetic simulation of a filter section indicates stray coupling qualitatively, while providing quantitative data for re-calibrating the circuit based results for final optimization.
he individual structures were integrated into larger super-structures, it was possible to leverage the EM Socket by choosing the Sonnet 3D planar EM solver. Selecting Sonnet as the primary solver takes advantage of unique features that assist in analyzing the complete diplexer layout. The Sonnet solver includes both a conformal meshing algorithm7 and an adaptive band synthesis algorithm8, which provides significant speed advantages that facilitate analysis of the entire LTCC structure. The final EM analysis provides for validation of the complete design; however, the variations in the manufacturing process still must be taken into account.
Statistical Design and Process Corners
Figure 8. The completed layout for a compact GSM/DCS diplexer can be validated using a variety of EM solvers accessible through the EM Socket interface.
Despite the fact that a complete EM simulation of the entire design structure meets specifications, this is by no means a guarantee the circuit will provide a high yield in a manufacturing environment. To verify that the design is reproducible, the statistical tolerances and distributions for all the underlying parameters in the network must be entered and either a Monte Carlo analysis or corner analysis must be run in order to see if the design remains within specifications under worst case conditions. It is especially important to consider variations in global parameters such as dielectric constant, layer thickness, and etching tolerance, as each of these parameters will affect many components in a correlated manner.
Figure 9. Final validation requires both full wave EM analysis and yield analysis to take into account manufacturing tolerances.
In this paper the use of a modern EDA architecture to facilitate the analysis of dense LTCC structures was demonstrated. Enabling technology included: an open product architecture that facilitated the creation of a robust LTCC PDK through user-defined electrical and physical models; discrete value optimization to efficiently take into account the effects of interconnect and parasitic layout issues with EM simulations; and an EM Socket interface to leverage third party solvers. In addition, simulation technologies were combined through space mapping to optimize the final design using both EM and circuit solvers. Lastly the statistical variations of the manufacturing process were incorporated in order to verify the manufacturability and yield of the final design.
1. Spoto, James, "Looking Beyond Monolithic Myopia," IEE Electronics Systems and Software (August/September 2003).
2. Moll, Francese, Interconnection Noise in VLSI Circuits (Boston: Kluwer Academic Publishers, 2004) 18-22.
3. M.B. Bazdar, A.R. Djordjevic, R.F. Harrington, and T.K. Sarkar, "Evaluation of quasi-static matrix parameters for multiconductor transmission lines using Galerkin's method," IEEE Trans. Microwave Theory Tech., vol. MTT-42, July 1994, pp. 1223-1228.
4. Rautio, James C., "Testing Limits of Algorithms Associated with High Frequency Planar Electromagnetic Analysis," (paper presented at the European Microwave Conference, October 2003).
5. Martin Versleijen, "Design Technology Challenges for RF Modules", presented at the International Microwave Symposium, June 2003.
6. John Bandler, "Design Optimization of Interdigital Filters Using Aggressive Space Mapping and Decomposition", IEEE Transactions On Microwave Theory And Techniques, Vol. 45, No. 5, May 1997.
7. James C. Rautio, "A Conformal Mesh for Efficient Planar Electromagnetic Analysis", IEEE Transactions On Microwave Theory And Techniques, January 2004.
8. James C. Rautio, "EM Approach Sets New Speed Records", Microwaves & RF, May 2002
GLOSSARY OF ACRONYMS
DCS- Digital Communications System
DLL - Dynamic Link Library
EDA - Electronic Design Automation
EM - Electromagnetic
GaAs - Gallium Arsenide
GSM - Global System for Mobile Communications
IC - Integrated Circuit
IP - Intellectual Property
LTCC - Low Temperature Co-fired Ceramic
MMIC - Monolithic Microwave Integrated Circuit
MOM - Method of Moments
PCB - Printed Circuit Board
PDK - Process Design Kit