Optimization of Metal-Metal Comb-Capacitors for RF Applications
Due to the large number of possible structural variations, the design and modeling of metal-metal comb-capacitors for RF and analog applications can be an arduous task. Using a rapid modeling process for these structures facilitates optimization.By Jay Rajagopalan and Haris Basit
Although capacitors are relatively "unglamorous" components, their significance in RF circuits should not be underestimated. Especially today, circuits are pushing the limits of technology and mixed signal is the norm, rather than the exception.
Figure 1. A cross section of the MMCC device described in this article. Colors represent the two different nodes of the capacitor. The bottom plane represents the substrate ground.
Cutting-edge technology-based hi-rel, precision and tight-tolerance capacitors can be found in resonant circuits and filters, VCOs, coupling between stages and bypass applications, just to mention a few. The characteristics by which such capacitors are judged include capacitance density; parasitic capacitance to ground; quality factor; voltage, temperature, and frequency coefficients; and the maximum allowable peak repetitive voltage.
Building and optimizing a MMCC involves a number of complex tradeoffs. There are a large number of possible topologies and each topology has several tunable parameters. Furthermore, the optimum tradeoffs derived for a 0.25μ process may not be optimum for a 0.18μ or smaller process. It becomes impractical to fabricate and measure all the possible variations. Thus, extraction software was utilized to simulate numerous variations of which only a small subset were fabricated and measured to validate the software and methodology.
For the techniques presented in this article, the simulation software used is RF-PASS. It is suitable for this application because it is specifically designed to model large distributed passive structures for RF applications using full 3-D field solvers. However, it is by no means the only software capable of performing such functions.
Figure 2. Effect of scaling on capacitance and parasitic capacitance.
The software is capable of extracting fully distributed and coupled resistance, capacitance, and inductance (self and mutual) models of all conductors. In addition, the software includes parameters important to RF applications such as skin effect and induced currents in the substrate. A detailed frequency dependent SPICE model is created and this model is used to generate S- and Z- parameters. Inductance modeling of capacitors can also be included to predict the self-resonance frequency.
In commercial CMOS or BiCMOS processes the following capacitors are generally available:
Capacitors that use the MOSFET gate oxide2
Poly-insulator-gate poly (Double Poly) capacitors2
Currently, the highest capacitance densities are obtained with capacitors that utilize MOSFET gate oxides. Capacitance density of 6 fF/μ2 has been reported2. However, there is a trade-off between the gate oxide thickness and the breakdown voltage. A 50-Angstrom gate oxide capacitor in a 0.25μ process can typically withstand a maximum peak repetitive voltage of 2.75 VDC. Depending on the topology and circuit design this may be a limitation. The CV characteristic varies with the particular process technology and is non-linear. This non-linearity may cause distortion in the circuit.
Figure 2. Effect of scaling on capacitance and parasitic capacitance.
To minimize parasitic capacitance to ground, MIM capacitors are typically built near the top of the metal stack; for example, a bottom-plate using METAL4 and a top-plate using METAL5 separated by a thin insulator layer a few hundred Angstroms thick. The large separation between the bottom plate and substrate (?6μ) helps in reducing the parasitic capacitance to ground to about 2% of the useful inter-metal capacitance (trans-capacitance). MIM capacitors have very good voltage and temperature-coefficient characteristics and a capacitance density of approximately 0.8 fF/μ2. MIM capacitors are available in many RF CMOS and BiCMOS processes, however, they require extra masking steps to implement and increase the cost of the IC. Furthermore, these devices do not scale with process technology.
Double-poly and MOS capacitors also have parasitic capacitance associated with them. Double-poly capacitors have about 18% parasitic capacitance to ground while MOS capacitors can have around 2% to 20% parasitic capacitance to ground depending upon their design. Both MOS and double-poly capacitors have the problem of very high series resistance to one of the two nodes.
MMCCs hold much promise in providing capacitors that continue to improve with succeeding process technologies. Capacitance density increases significantly as the number of metal layers increase and the feature size decreases. Such capacitors can be optimized to minimize parasitic capacitance and to make the parasitic capacitance symmetric, thus reducing noise pickup from the substrate or nearby structures.
Various MMCC topologies of capacitors have been reported in literature5,6,7,8,9. In this work, the topology shown in Figure 1 is used6. In general the topologies can affect the capacitance density by trading off capacitance from three sources: 1) Parallel plate capacitance between conductors on two different metal layers (vertical fields). 2) Parallel plate capacitance between two conductors on the same metal layer (horizontal fields). 3) Fringe capacitance that cannot be attributed to either of the two preceding sources (fringing fields). While useful as a conceptual model, for feature sizes below 1.0μ, this simple model must be replaced with a full 3D field solver to get accurate results.
Each topology also has many tunable parameters. Only after optimizing these parameters for each topology can one properly compare the various topologies. One must choose which metal layers to use, how long and wide the fingers should be and how to connect the fingers together. These choices will affect capacitance density, parasitic capacitance and quality factor.
Choosing to omit metal layers near the substrate reduces parasitic capacitance to ground but also decreases the capacitance density. Narrow fingers and spacing have larger capacitance density but increased resistance that reduces the quality factor. The optimum length of a finger is dependent on the resistivity and width of the finger. To model the capacitor near self-resonance the inductance and mutual inductance of the fingers and leads must also be included. The location and number of vias used to connect metal layers that form part of the same node are also important parameters. One can greatly increase the series resistance by an improper placement of vias.
Prior work has shown MMCC devices with a capacitance density of 0.53 fF/μ2- in a 0.25μ process technology. The capacitance density depends on the topology of the finger structure used. In this article, MMCCs are shown to produce a capacitance density of 0.61fF/μ2 on a 0.25μ technology. Much higher capacitance densities are predicted for finer lithography processes (See Table 3).
The MMCCs discussed in this article have a parasitic capacitance of 4% from each node of the capacitor to ground. As both nodes are almost equally coupled to ground, substrate noise is not readily picked up by the capacitor. Capacitors based on finer lithography processes can achieve a parasitic capacitance of less than 0.5% per node.
The Q-factor is a measure of the useful energy stored in the capacitor versus all other energy loss mechanisms. The energy loss mechanisms include energy dissipated through resistive losses in the conductors and substrates and the energy siphoned into the parasitic capacitances. Care needs to be exercised in comparing Q factors as they are a function of the value of the capacitance and frequency. MIMs and MMCCs of 500fF have a Q > 80 at 2.4 GHz.
Modeling of MMCCs
MMCCs of various physical dimensions were laid out. The inputs required to RF-PASS are the GDSII layout and a process technology file. The process technology file contains information on thickness and resistivity of substrate layers; thickness and resistivity of conductive layers; and thickness and permittivity of dielectrics. The inputs are read into RF-PASS after which the nets and nodes can be identified using the graphical user interface. The output of RF-PASS consists of a SPICE file containing thousands of distributed resistance, capacitance, inductance and mutual inductance elements. Many of these elements are frequency dependent. This spice deck is then solved for Z-, Y- and S-parameters over a user selected frequency range. The user may also select to have the software find a lumped element model that best fits the Y parameter data.
One example layout is an MMCC with the following characteristics: 35 fingers (18 for Net1 and 17 for Net2), the length of each finger is 26μ, the width of each finger is 0.4μ, and the spacing between fingers is 0.4μ. The capacitor structure was constructed using Metal layers 1 through 5 in a 0.25μ, 5-metal layer process. The summarized report for this device is shown in Table 1.
Table 1. Net to Net Coupling Capacitance:
|Net 1 Net 1:||3.1429e-14|
| Net 1 Net 2:
|Net 2 Net 2:||3.1368e-14|
|Net to Substrate Capacitance|
|Net 1 Substrate:||1.7490e-14|
|Net 2 Substrate:||1.8724e-14|
Layer by Layer breakdown for Net1
|All Layers||5.0900e-13 100.00%|
|Metal 1||1.0103e-13 19.85%|
|Metal 2||1.0505e-13 20.64%|
|Metal 3||1.0025e-13 19.70%|
|Metal 4||1.0219e-13 20.08%|
|Metal 5||1.0378e-13 19.74%|
Layer by Layer breakdown for Net2
|Metal 1||1.0376e-13 20.34%|
|Metal 2||1.0017e-13 19.63%|
|Metal 3||1.0518e-13 20.62%|
|Metal 4||9.7283e-14 19.07%|
|Metal 5||1.0378e-13 20.34%|
Quality Factor and Capacitance Density
|Q @ 1.58 GHz = 257 (initial result)|
|Q @ 1.58 GHz = 37 (including contact vias)|
|Cap. Density = 460fF/27.52 = 0.6fF/2|
|Parasitic Capacitance = 7.8%|
|Simulation results. Net1 and Net2 refer to the two nodes of the capacitor. All capacitance values are in Farads.|
The tool provides information on the Q of the structure, the contribution of each metal layer to overall useful capacitance as well as the parasitic capacitance. Note that in the first part of Table 1 capacitance from a net to itself is listed. This capacitance is due to the distributed nature of the extraction allowing one segment of the net to couple to another segment of the same net.
The test structures were fabricated in a 0.25μ 5-metal layer process. Measured results from one structure are shown in Table 2. The measured values of trans-capacitance and parasitic capacitance matched the RF-PASS simulation results very well. However, there was initially a big difference in the measured vs. modeled Q. This discrepancy was due to an omission of the contact structure for each terminal from the RF-PASS simulation while not concomitantly adding it to the de-embedding structure for measurement. Thus these contacts became part of the measured results and not part of the simulated results.
Table 2. Measurement Results
|Parameter @ 2 GHz||Measures Values|
|Trans-capacitance - C12||4.67e-13 F|
|Port 1 Cap. to ground||2.00e-14 F|
|Port 2 Cap. to ground||2.00e-14 F|
|Series Resistance - R12||5.57|
|Q factor at port 1 - Q11||34.5|
|Q factor at port 2 - Q22||52.0|
|Q factor after via-R
The contacts consist of 6 parallel via stacks from METAL5 to METAL1. The resistance of 6 parallel vias stacks in each terminal was about 2.5Ω for a total series resistance of 5.0Ω. This is significantly greater than the intrinsic finger resistance. Adding the contact structure to the RF-PASS simulation easily compensated for this oversight. The new RF-PASS Q value was predicted to be 37. This matches closely with measured data. Alternatively, de-embedding via resistances in the measurement yielded a Q of 212. This also matches closely with a Q of 257 computed by RF-PASS.
Scaling with Process Technology
The layout simulated earlier was scaled to create the additional layouts given in Table 3. The width, length and spacing of fingers were all scaled. Metal and dielectric thicknesses were not changed. As the width and length of the fingers were scaled by the same value, the resistance of each finger will remain approximately constant. The area shrinks very rapidly with the square of the scaling factor. The smallest finger width and spacing used is 0.08μ which corresponds to a finger length of 5.2μ and an area of 31μ2. The largest finger width and spacing used is ten times larger at 0.80μ, ten times longer 52.0μ, and one hundred times more area 3091μ2.
|Finger W/S( )
||Finger L ( )||Capacitance (fF)||Density (fF/2)||Parasitic Cap (%)|
|Several scaled layouts of the thirty-five-finger comb capacitor were built. Metal and dielectric thicknesses were not scaled with horizontal dimensions.|
It can be seen from Figure 2 that parasitic capacitance varies strongly with area. However, the capacitance between the two nodes (trans-capacitance) tends to flatten out as we decrease the area. For narrow finger width and spacing (< 0.3μ) It is possible to get very high capacitance densities approaching that of gate oxide capacitors while simultaneously getting parasitic capacitance rivaling MIM capacitors. Reliability and voltage withstand capabilities of capacitors with such reduced dimensions could be affected, but have not been analyzed in this article.
MMCCs offer good capacitance density, Q, parasitic capacitance and voltage withstand abilities. The topology chosen here has a capacitance density of 0.61fF/μ2, a Q of 200 and 8% parasitic capacitance to ground. A simulator capable of quickly modeling all relevant effects including substrate currents, skin and eddy current losses must be used to find an optimum device. A good correlation between simulation and measurement is seen. Given the intrinsically low resistance of the MMCC structure, care needs to be taken to minimize via and contact resistance in the circuit. Future process technologies with the concomitant decrease in metal finger spacing and metal finger width will enable the capacitance density, parasitic capacitance and quality factor values to rival the best on-chip capacitors available.
The authors would like to thank Linda Smith, Tikno Harjono, Jeff Huard, Kyuwoon Hwang and O. Ersed Akcasu for their contributions to modeling, characterization and simulation.
Jay Rajagopalan received his BSEE from the University of Madras, India in 1987, MSEE from the Indian Institude of Science in 1991 and MSEE from Virginia Tech, Blacksburg, VA in 1993. He is a Staff Circuit Design Engineer at National Semiconductor's RF Products Group in Federal Way, WA. He was with Mitsubishi Electric Corp, Kobe, Japan from 1990~91 designing embedded microcontroller software, and with the Virginia Power Electronics Center, Virginia Tech from 1993~1997 working on the International Space Station power management designs and on IC design for power factor correction. He has worked at National Semiconductor since 1997 on the design of high performance RF and power management ICs and has been awarded 4 patents in these areas.
Haris Basit worked on the design of surface emitting ultra bright LEDs using advanced eptiaxial growth techniques while a graduate student at the University of Illinois, Urbana. Later, at IBM he worked on Hetrojunction bipolar Transistor (HBT) technology in a joint development project with Rockwell. Following this, he joined Rockwell to work on HBT and MESFET circuits and processes. During his tenure at Rockwell, Mr. Basit also managed a DARPA program for the design of advanced EDA software focused on High Speed Design. Subsequent work at Bell Labs involved introduction of Formal Model Checking software. Mr. Basit is currently VP of Business Development at OEA International where he manages development of EDA software targeted for RF and analog design.
 OEA International, Inc., RF-PASS Modeling Software Guide, June 2001
 National Semiconductor Corporation, 0.25um CMOS Process Electrical Design Rules and Characterization Data, May 2001.
 TSMC, CMOS RF/Mixed-Signal 0.25um process design guide, 2000
 Jeffrey A. Babcock, et. al, "Analog Characteristics of Metal-Insulator-Metal Capacitors using PECVD Nitride Dielectrics", IEEE Electron Device Letters, vol. 22, No. 5, May 2001, pp. 230-232
 Tridad Sowlati, Vickram Vathulya, Domine Leenaerts, "High Density Capacitance Structures in Submicron CMOS for Low Power RF Applications", ISLPED 2001, Huntington Beach, CA, pp. 243-246.
 O. E. Akcasu, "High Capacitance Structure in a Semiconductor Device", U.S. Patent 5,208,725, May 1993
 Hirad Samavati, et. al, "Fractal Capacitors", IEEE J. of Solid State Circuits, vol. 33, No. 12, Dec. 1998, pp. 2035-2041
 Roberto Aparicio, Ali Hajimiri, "Capacity Limits and Matching Properties of Lateral Flux Integrated Capacitors", IEEE 2001 Custom Integrated Circuits Conference, pp. 365-368.
 Kare Tais Christiansen, "Design and Characterization of Vertical Mesh Capacitors in Standard CMOS", 2001 Symposium on VLSI Circuits Digest of Technical Papers, pp. 201-204.
Glossary of Acronyms
BiCMOS - Bipolar CMOS
CMOS - Complimentary Metal-Oxide Semiconductor
MIM - Metal-Insulator-Metal
MMCC - Metal-Metal Comb Capacitors
MOSFET - Metal-Oxide Semiconductor Field-Effect Transistor
VCO - Voltage-Controlled Oscillator