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Embedding Passives

Mon, 03/08/2004 - 12:26pm

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EM solvers coupled with fast algorithms — an efficient solution to analyzing embedded passives.

By Ernest Worthman, Technical Editorial Director

Like it or not, today's technology mantra is smaller, lighter, faster, and feature-flush. And the only direction that can lead is to miniaturization.

Unlike semiconductors, where size isn't as closely tied to frequency, with passives, size matters, albeit with some more than others. Embedded passives offer up designs with increased reliability, improved performance, reduced board real estate, and lower cost.

Capacitors and resistors represent the majority of passive components used today (inductors are a bit harder to embed). Passives typically account for up to 90% of the components and up to 40% of the board space. Is it any wonder why embedding passives is a hot topic for the 21st century?

However, all that glitters isn't always gold. There are a number of technological roadblocks facing embedded passives.

Most significantly, substrate fabrication costs — be it ceramic, laminate, or thin film — increase when embedding passives. Therefore, yield takes on a new perspective. Second, considering the amount of variables with embedded passives, efficient design methods are critical.

On the other side of yield equation is the fact that the overall area of the substrate will decrease when embedded passives are used. This implies improved yield densities and can offset the increased substrate and waste costs.

Another plus for embedding is reliability. We are all aware of the logarithmic improvement in reliability with large-scale integration. Extrapolation tells us such improved reliability can be realized with embedded passives as well, since electrical connections are fewer and shorter and solder joints are reduced, as well as other advantages such as reduced external component counts.

So, given just the above few points, it is obviously advantageous to embed passives, using as efficient a design process as possible.

One such approach is to use the lumped circuit model approach, with a bit of a twist. Since the fundamental lumped model approach is computationally intensive and somewhat trial and error, an alternative, synthesized approach that involves fast algorithms, combined with the Chauchy method and full wave EM solvers has been presented. This well documented, in various forms, approach can generate a decent interpolated response with a minimum of frequency points, cutting hours off of the analysis time.

Now, considering I've only got the rest of this column to present this, I'll just touch on the highlight. The full technique is presented in [1].

First thing is to generate the device's transfer function in the frequency domain:

Where: s = jω, ak and bl are complex coefficients and H is admittance, impedance or scattering parameters.

Rewriting the equation:

and developing the matrix form of this equation is represented by: [A] [x] = 0, where:

and [x] is a solution vector that contains all of the coefficients of H(S) as follows: [x] = [a0 a1 ... aP b0 b11 ... bQ]T. And l ... m are the frequency points with m <= P + Q+2.

As elaborated in [1], one examines the non-zero singular values as possible frequency points. And, since the matrix is generated though a set of data points, it doesn't involve derivatives. Therefore it can be used by the EM solver to find the passives values fairly quickly, compared to other empirical techniques, and find P and Q. Once P and Q are found, the equation:

produces eigenvectors ak and bl, corresponding to minimum eigenvalues in this equation, and H is the complex conjugate of the matrix. Solving this equation presents a least squares solution, that can be applied to the fast algorithm process.

A full analysis is presented in [1] as well as the procedure for applying the fast algorithm.

1. K. L. Choi and M. Swaminathan, "Utilization of Fast Algorithms to Analyze Embedded Passive Components using Commercial EM Solvers", Proceedings of the 6th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 27-29, San Jose, California, Oct. 1997.

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