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Simulation-Oriented Design of Power Dividers

Mon, 02/02/2004 - 6:52am

Microwave systems often need distributed RF power to various paths, for multiple applications. The easiest way to accomplish this is with power divider circuits. Working with simulators for low-frequency lumped element power dividers helps the engineer design the optimum product, at the lowest cost and with minimum aggravation. By Anurag Bhargava

The 2-way (3 dB) power divider can be thought of as a three-port circuit, which is symmetrical about the horizontal axis (See Figure 1.1). All ports are terminated in an identical resistance R. Such a circuit can be used as power divider if Port 1 is used as the input port with port 2 and port 3 being output ports. The same circuit can act as a power combiner if the input is applied at ports 2 and 3, and the output is taken at port 1 (See Figure.1.2). The "A networks are identical and should have impedance transforming property such that when two arms are connected in parallel, they show a matched input source resistance R. The element denoted by Zm is a mutual coupling element used to isolate ports 2 and 3.


Figure 1.1 Symmetric 3-port circuit used as a power divider.


Figure 1.2 Synthesized Impedance Transforming Filter of section 1.

N-way Power Divider

One common approach to building N-way power dividers is a tree structure. This structure consists of individual two way dividers connected in a tree-type topology (See Figure 2). The layout shown in Figure 2 is for a 4-way power divider. Another 2-way section can be added in each output branch to make it an 8 way power divider, and so on. (Note: each added network should be identical. (viz., A1, A2 etc.) for equal power division in these adjacent branches.)

Synthesis of N-way Power Divider

The design of an N-way power divider requires that individual sections be considered and designed separately.
The first section, A1, shown in Figure 2 — from node 1 to node 21/22 can be modeled as an impedance-transforming filter. Impedance transforming lumped or distributed element, lowpass, highpass or bandpass filters, or simple lumped element narrowband impedance matching elements can also be used as impedance transforming circuits. In that case, the isolation impedance Z m has to be found and evaluated specially for the selected impedance matching filter.


Figure 2. Tree-type 4-way power divider

The impedance, Z m , may involve resistance, self or mutual inductance and/or capacitance, depending on the selected impedance transforming filter.
The synthesis of individual impedance matching filters, denoted by A1 and A2 in Figure 2 should be done by keeping the source impedance at 100Ω . This is required so when two identical matching filters are connected in parallel they will match to 50Ω source. Load impedance should be kept at 50Ω?in an ideal system until, and unless there is some specific requirement of some other finite load impedance. Such impedance deviation usually depends upon the input impedance of system, which is to be connected at the output port. The isolation impedance is then calculated depending upon the matching network topology used.
Similar impedance transforming filters/networks can be added in each output branch to make a 2-way power divider a 4-way, 8-way, and so on. Isolation impedance ( Z m1 , ZM m2 etc. ) will be determined, by circuit requirements, and tuned accordingly. After integrating all of the sections the element values can be further be optimized. This is done to obtain better return loss at all of the ports, and better insertion loss and greater isolation between the output ports. Inherent distribution loss associated with the ideal N-way power divider can be given by: Distribution Loss = 10*log10(1/N) dB.
Any additional loss is the insertion loss of the power divider. Any variation in total loss along different paths is known as amplitude imbalance. Any variation in phase along different paths is known as phase imbalance.
The theoretical distribution loss for various power dividers is summarized in Table 1.

Table 1
Number of Theoretical
Output Ports (N) Distribution Loss (dB)
2 3.0
3 4.8
4 6.0
5 7.0
6 7.8
8 9.0
10 10.0
12 10.8
16 12.0
24 13.8
48 16.8

Designing the 4-way Power Divider

The design described is of a 250 MHz 4-way power divider.
The software used to model the design is E-Syn from ADS2002. The synthesis parameters for the impedance transforming filter of section 1 (the path from node 1 to 21 in Figure 2) entered is: frequency as zero to 0.3 GHz; source impedance is 100Ω and load impedance is 50Ω. The filter type was selected is a Chebyshev low-pass filter with 0.1 dB of ripple.
The synthesized filter for section 1 with synthesized element values is shown in Figure 3 (a). The source impedance was kept as 100Ω and load impedance as 50Ω. Results for the section 1 filter are shown in Figure 3 (b). The circuit shown in Figure 3 (a) was synthesized and simulated with ideal elements, which do not take component's finite Q into account. Therefore, the circuit elements were replaced with the actual library components available in ADS2002.


Figure 3(a) Synthesized Impedance Transforming Filter of section 1.


Figure 3(b). Response for Fig. 4(a).


Figure 4(a) Synthesized Impedance Transforming Filter of section-1 with Library Elements.

The circuit with library element is shown in Figure 4 (a) and the result is shown in Figure 4 (b).
The source impedance for individual channels was kept to 100Ω?for the simulation because, as described in paragraph 3, when this filter is connected in parallel, for equal power division, this parallel combination should match to source impedance of 50Ω.
The individual channels can now be them (See Figure 5 (a)). One more inductor, L3 @10nH, was added to optimize the input return loss. The component values in Figure 5 (a) are same as in Figure 4 (a). An isolation resistor with a value of 100Ω was added across the two output terminals to provide sufficient isolation. The return loss and insertion loss of the output is shown Figure 5.1 (b). The isolation of 30 dB can be seen between two output ports in Figure 5.1 (c).
Finally, the 2-way power dividers are connected in each of the output branches of the circuit shown in Figure 5.1 (a). This configures the 4-way power divider.


Figure 5.1(b) Return loss and insertion loss of 2-way power divider.


Figure 5.1(c) Isolation for a 2-way power divider.


Figure 6.1. Complete schematic of the simulated and tested 4-way power divider.


Figure 6.2 Complete layout for the simulated and tested 4-way power divider.


Figure 6.3. 3D-view of the simulated 4-way power divider.

The impedance transforming filter component values remain unchanged. The complete schematic of simulated 4-way power divider is shown in Figure 5.1 (c). The values of the output section isolation resistors and series inductors between section 1 and section 2 - 3 are tuned to get the required isolation and return loss, respectively. The circuit was fabricated on a 1.6 mm FR4 board substrate, and the simulated results incorporate the effects of the actual mounting pads provided for the Piconics PA series chip inductors, ATC 100A series chip capacitors and Vishay DALE 0805 series chip resistors. The Complete schematic and layout for the simulated 4-way power divider is shown in Figures 6.1 and 6.2 respectively. Mounting pads and tracks for chip components are kept hidden in schematic diagram shown below to maintain clarity. Figure 6.3 depicts the 3D-view of the simulated 4-way power divider.

Simulated & Measured Results

The simulated results are shown in Tables 2.1 to 2.3 and measured results are shown in Figures 7.1 to 7.3, simulated and measured results for 4-way power divider are summarized in Table 2.4 which shows excellent matching between them.


Figure 7.1. Measured input return and insertion loss.

Table 2.1. Input/Output Return Loss

freq
dB(S(1,1)) dB (S(2,2)) dB (S(4,4)
250 MHz -19.78 -21.46 -21.41

Table 2.2. Insertion Loss

freq
dB (S(2,1))
dB (S(4,1))
250.0 MHz -6.740 --6.735

Table 2.3. Isolation in Adjacent Outputs


freq
(S(2,3))
250.0 MHz -18.834

Table 2.4
Parameter Simulated Value Measured Value
S(1,1)
-19.78 dB - 29.9 dB
S(2,2)
-21.46 dB -25.03 dB
S(2,1)
—6.74 dB -6.65 dB
S(4,1)
-6.735 dB -6.6 dB
S(2,3) -18.83 dB -20.66 dB
Anurag Bhargava is a Scientist/Engineer-SD, MSTD/MSG, Space Applications Centre, Indian Space Research Organisation (ISRO), Ahmedabad (Gujarat) - 380 015, India. He can be contacted at anuragbhargava@rediffmail.com. The author wishes to extend his gratitude to Shri S.S. Rana, Shri. V.H.Bora and Shri. C.V.N Raofor their interest and guidance in the mentioned work.
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