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High-Speed ADC Specs for Wireless Applications

Mon, 11/24/2003 - 7:51am

By Debbie Brandenburg, Signal Conditioning Group, Fairchild Semiconductor

The analog-to-digital converter (ADC) is an essential element in many of today's wireless communications applications that require optimum noise characteristics. A typical transmit/receive chain is represented in Figure 1. In this example, the incoming RF signal is down-converted to IF (or baseband) with a series of bandpass filters, low noise amplifiers, and local oscillators. The analog signal must then be converted to digital with an ADC before processing by the DSP. The purpose of the ADC is to digitize the complex waveform so that a DSP or ASIC can perform the demodulation. Often, two ADCs are used to sample the quadrature signals to extract the I and Q signal components for processing. In many cases, there are hundreds of signals at various intensities that are received by the antenna. But there are key considerations in this process. For instance there is inherent noise associated with the antenna and each segment of the signal chain. It is important that the noise introduced by the ADC be understood and the ADC have the capability to determine signal from noise.


Figure 1. A typical ADC transmit/receive chain.

Signal vs. Noise

In baseband sampling applications, the dynamic performance of the converter is not critical because the signals being sampled are low frequency and band-limited. Since the signal component is at DC, specifications such as gain and offset are important. For example, if a baseband converter has a large DC offset, this would appear as an unmodulated carrier directly on top of the signal of interest. If the signal is large enough, it could completely block the desired carrier. Baseband ADCs can be low-cost, low-power, low-sample-rate devices.

In IF sampling applications, all RF signals are converted to lower frequencies for easy detection. Many communications applications have IF frequencies as high as 250 MHz and require 10 to 14-bit ADCs with greater than 65 MSPS speeds. The ADC must have fast clocking rates and very wide input bandwidths in order to accommodate these higher IF frequency signals. WCDMA applications utilize a multicarrier platform to digitize hundreds of signals at once. It is important that the converter not generate spurious signals that interfere with the desired signals. These spurious signals can be in the form of harmonics or intermodulation products, resulting in poor receiver performance.

ADC Specifications

In IF sampling applications, ADC dynamic performance is critical and plays a direct role in the overall sensitivity of the receiver. The two key ADC specifications are signal to noise ratio (SNR) and spurious free dynamic range (SFDR).

SNR is a measure of the broad band noise that is introduced into the signal through the ADC and the sampling process. The magnitude of the input is compared to the sum of all other frequencies, except for those representing harmonics of the fundamental frequency. The ratio of the signal to the sum of the noise bins is the SNR. SNR is a specification usually provided by the ADC manufacturer. If a data sheet is not available, SNR can be approximated by SNR = 6.02N + 1.76, where N is the effective number of bits (ENOB). SNR can be used to determine the input noise voltage of the ADC and thus the noise contribution to the signal path.


Figure 2. An ADC's 77dB SFDR

SFDR is defined as the difference between the rms value of the amplitude of a single tone and the rms amplitude of the worst spur as the tone is swept through the entire ADC input range. The FFT shown in Figure 2 illustrates a 77dB SFDR. SFDR will determine how well the receiver performs as the signals approach the noise floor.

Once an ADC has been selected, it is important to follow basic layout and grounding guidelines to prevent that perfectly selected ADC from causing problems. Separating the analog from the digital portions of the board and maintaining straight signal paths would be ideal. With board sizes getting smaller and smaller every year this ideal situation may not be entirely possible. Following some basic guidelines will help get the best performance from high speed ADCs.

Tips on Board Layout

The board layout will have profound effects on the ADC's performance. Key areas of concern are the clock and analog input paths. Make the clock input path as short as possible and kept as far as possible from other signal traces. If the clock must cross another trace, cross at a 90° angle to minimize coupling. In high frequency applications, crossing noisy digital paths, even at 90°, can still cause unwanted jitter. As a precaution, avoid crossing analog and digital traces all together. If using a differential clock, keep the trace lengths equal in order to cancel the capacitive coupling of the clock to the input. Avoid running the analog input trace near digital signal paths. Routing the analog input near or parallel to digital signals will degrade the quality of the signal seen at the ADC's input. Use an analog ground and a digital ground. Do not run the digital ground plane under analog circuitry, such as amplifiers and clock buffers.

In general, a good layout will begin with a low-impedance ground plane, short connections in and out of the converter and proper supply decoupling.

Conclusion

The key to selecting a high speed ADC is to understand the system where it will be used. In many wireless applications such as IF sampling receivers, the most important contributing factor of the ADC is noise and dynamic range. In order to maintain the ADC's SNR and SFDR performance, proper layout, grounding, and supply bypassing are essential.

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