Inductor device generators offer efficiency in RF IC design.
By Marko Suominen, Mentor Graphics
An integrated, easy-to-use RF IC design flow is an important element in meeting the project requirement. An important challenge presents itself in post-layout verification, where many secondary effects impact the quality and performance of the complete design. In situations where rapid pre- to post-layout turnaround is key to meeting project deadlines, new scenarios must be investigated, and trade-offs need to be made during the design and verification process.
In this article, we will introduce inductor device generators, which offer a new level of efficiency in the development and automation of RF IC design, layout creation, and verification. The flexibility and ease-of-use of these device generators fit into the RF, Analog, and Mixed-Signal IC Design flow.
RF and Analog Mixed-Signal IC Flow - An Overview
The integrated IC design flow shown in the figure below has a few highlights:
Consistent Database - Same schematic for simulation, layout, and verification.
Consistent User Interface - Time domain, RF, and mixed-signal simulations are performed from the same environment (no change in user interfaces and no database transfer needed).
Unique Foundry Support - One library for each of the simulation models, process files, and DRC, LVS, and LPE rule files.
Schematic Driven Layout - Transfers schematic connectivity and instance data to the layout and drives layout generation and routing automatically, while the user can specify the desired degree of automation.
Implicit access to Device Generators - Create consistent and correct layout automatically with the flexibility to customize devices and use custom editing features to change the layout. Devices include MOS, resistor, capacitor, inductor, guardband, and more.
To meet the challenges of emerging technologies fueled by second and third-generation wireless systems, GPRS, 3G, Bluetooth, and HomeRF to name just a few, today's RF designs are seeing increasingly stringent specifications.
System-on-chip approaches, smaller applications, and increasingly dense chip areas significantly increase unwanted coupling. These factors, together with decreasing power supply levels, have brought differential topologies into the mainstream today. By using the right physical design products, symmetrical differential inductors can be implemented with an Inductor Device Generator. The symmetrical differential inductor consumes less chip area than conventional devices by combining two inductors into an area normally occupied by a single device. By taking advantage of the resulting increased mutual inductance the device size can often be reduced even further.
Design optimization can be achieved by altering the inductor width and spacing. For instance, the smaller area occupied by the inner turns increases the current density in the edge of the inner turn track and thus the inner turn can be narrower than the other turns. In order to keep the current density of the inner turn positive, the spacing to the adjacent turn should be relatively large. The outer turns form most of the inductance and thus narrow spacing is desired and wide wiring is used to minimize serial resistance. With an Inductor Device Generator, the width and spacing can be specified per turn.
Substrate resistance, Rsub can be decreased with a conductor plate under an inductor. Reducing Rsub increases the Q-value especially after resonance frequency. However Eddy currents, which occur in the solid conductor are detrimental to the Q-value. Using a Inductor Generator, radial slits can be added to the conductor plate which kill the Eddy current loops. The current flow in the inductor is not affected because the slits are perpendicular to the current flow. The increased parasitic capacitance can be utilized to help form the capacitor in an LC-tank.
A few of the key capabilities of a Inductor Device Generator:
Symmetrical differential inductor.
Spiral square, octagonal, or round coils also fully supported.
Optional patterned ground plane for improved Q.
Built in guardbanding.
User-specified diameter, number of windings, spacing and width of layers by push-button.
Variable space and width per turn input choice.
Simple, fast technology set-up for layer/multilayer definition.
Octagonal symmetrical inductor with patterned ground plane; loops = 6; d = 100 um; width = 4 um, 6 um, 8 um, 10 um, 12 um, 14 um; space = 8 um, 6 um, 4 um, 2 um, 10 um.
Square spiral and stacked inductor with guard band; loops = 3.5; d = 50 um; width = 5 um, 10 um, 15 um; space = 8 um, 6 um, 4 um.
16-segment spiral inductor with the guard band and the height offset (10 um); loops = 3.25; d = 80 um; width = 10 um, 12 um, 15 um; space = 10 um, 5 um.
Advantages Versus Hand Crafted Layout
Many aspects of manual layout of inductors make the efficiency of an automatic layout generator very desirable:
It is difficult to draw symmetrical layout by hand with accurate angles and points snapped to grid. The layout generator can produce DRC-correct geometry, meeting the specified design rules in a fraction of the time taken by hand.
Built-in contact generation makes DRC-correct connections and guard banding easy.
Adjustment of the inductor parameters during the optimization phase no longer introduces extra delays into the design cycle.
The layout generator can be accessed interactively from within a layout tool or driven directly from the schematic design, incorporating connectivity and ensuring correct-by-construction design.
Contrary to alternative techniques for automatic layout creation, which might involve copying geometry around planes of symmetry, the layout generator does not rely on a 'sample' layout as a source for a device variation or a new process. Porting the inductor to a new process simply requires the modification of a few variables for layer naming, rule definition and style control, all of which can be completed in a matter of minutes.
Extraction and Analysis
The device generator incorporates equations to calculate the inductance value. Additionally 3D solvers such as Sonnet EM analysis can be employed to carry out detailed evaluation. In this design flow, a menu-driven interface is available, which allows Sonnet to be opened directly on a selected layout. From here, an s-parameter file or SPICE netlist equivalent circuit can be generated automatically and can be incorporated into simulation. The user can also enter an interactive analysis session in Sonnet.
Marko Suominen has worked at Mentor Graphics in the position of Application Engineer for Integrated Circuits and Analog Mixed Signal products. Mr. Suominen can be reached at firstname.lastname@example.org.