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Designing With Low-Power High-Speed ADCs

Mon, 12/02/2002 - 6:27am

Architectural advances lead to focus on the ADC's auxiliary circuitry.

By David Nairn, Analog Devices, Inc.

     Recent architectural advances are enabling the development of high-speed/high-resolution ADCs with very low power dissipation. These advances are leading to the need for designers to pay close attention to the ADC's auxiliary circuitry.

     Traditional high-speed ADCs were based on the flash architecture. An N-bit flash ADC required 2N-1 high-speed comparators. Hence, the flash architecture was very power hungry for high resolutions. Newer high-speed/high-resolution ADCs use pipelined architectures. In the simplest case, a pipelined ADC requires one comparator per bit. Consequently, an N-bit pipelined ADC only requires N comparators, leading to very low-power high-speed/high-resolution ADCs. For example, the AD9071, a 10-bit 100-Msps two-step flash ADC required 620 mW, while the newer AD9215, a 10-bit 100-Msps pipelined ADC, requires only 120 mW. Due to the significant reduction in the core ADC's power, the power required by the ADC's auxiliary circuits such as the digital outputs, the reference, and the input buffer has become significant. In addition, the more stringent noise requirements of higher resolution ADCs has made the noise generated in auxiliary circuits much more important. Consequently, to fully exploit the advantages of the newer ADCs, one must now consider the impact of the digital outputs, the reference structure and the input buffer on the system's performance.

     Due to the increased data rates of high-speed ADCs, Low-Voltage Differential Signaling (LVDS) is emerging as a viable alternative to CMOS output drivers. CMOS drivers pose two problems for high-speed/high-resolution ADCs. Firstly, CMOS drivers generate significant on-chip noise, which can degrade an ADC's accuracy. Secondly, CMOS drivers are limited to maximum clock rates of about 125 Msps, beyond which the data must be demultiplexed into multiple channels, which increases the pin count. In comparison, LVDS is a differential technique that minimizes on-chip noise and can be clocked at rates exceeding 500 Msps. Unfortunately, LVDS requires two pins and 3.5 mA of standing current for each output driver, leading to an increased pin count and higher power dissipation. A comparison of the CMOS and LVDS pin requirements for high-speed data rates is illustrated in Figure 1.


Figure 1. CMOS and LVDS Driver pins per data bit.

Above 125 Msps, LVDS does not impose a pin count penalty. Indeed at higher data rates, the pin-count and hence, the package size can be reduced with LVDS drivers. A comparison of CMOS and LVDS power requirements are illustrated in Figure 2.


Figure 2. CMOS and LVDS Driver power per bit.

At high data rates, the power dissipation of CMOS drivers can exceed that of LVDS drivers. Consequently, LVDS is the preferred choice for output drivers in high-speed/high-resolution ADCs, due to the reduced pin count, and the potential for lower power and improved accuracy.

     To generate an accurate output, ADCs require a reference. Most ADCs have an on-chip reference that consumes minimal power. Typically, provisions are made to override the internal reference, when the application requires either a different voltage or a more precise reference. Within a pipelined ADC, the reference is subdivided into a few well-controlled reference levels with sufficiently low impedance to drive large internal switched-capacitor loads quickly. The required low output impedances can be achieved with either on-chip buffers or with large off-chip decoupling capacitors. On-chip buffers are used in the highest speed ADCs to avoid problems with the series inductance of the package leads. This approach is used in the AD9430, a 12-bit, 210-Msps pipelined ADC. While an on-chip buffer reduces the pin count, it also consumes power. For lower speeds, the package's leads do not pose a problem. Consequently, the AD9235, a 12-bit, 65-Msps pipelined ADC, is able to use off-chip reference decoupling to help lower the ADC's power to 350 mW, without degrading the ADC's accuracy. While off-chip reference decoupling results in significant power savings, it is typically not viable for the highest speed ADCs.

     To achieve the ADC's stated accuracy, the ADC must be driven by an appropriate source. Internally, most pipelined ADCs use switched-capacitor sample-and-holds, as illustrated in Figure 3.
Figure 3. A single-ended switched-capacitor sample-and-hold.

The periodic switching of CH to the input generates signal dependent kickback. Consequently, ADCs typically require some form of input buffering to suppress kickback transients without band limiting the signal. In many lower speed applications, the ADC is preceded by an amplifier, such as a variable gain amplifier (VGA), that is capable of driving the ADC directly. Consequently, the AD9226, a 12-bit 65-Msps ADC has been designed without an on-chip buffer to minimize total system power. In some applications, the circuitry preceding the ADC is unable to drive the ADC directly. In these cases a buffer must be added to drive the ADC. This problem becomes more important at both higher speeds and higher resolutions. To simplify the driver requirements, high-speed pipelined ADCs, such as the AD9432, a 12-bit 105-Msps ADC include a buffer on chip. This buffer/ADC combination reduces the required board space and power of the total system while improving the ADC's accuracy.

     To fully exploit the high resolution and low power dissipation of the new high-speed ADCs, one must now consider the impact of the digital output drivers, the reference structure, and the input buffer on the system's performance. For each of these auxiliary circuits, the choices affect the system's overall power dissipation, board size, and accuracy.

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