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SoC Test Cost Reduction Seminars

Tue, 11/12/2002 - 6:06am
This seminar is for ASIC/SoC design, test and production engineers and managers. The seminars cover major DFT technologies that reduce SoC test costs and include product demonstrations. The technologies covered in the seminar include: "Virtual" scan for extremely compressed scan-test patterns; True "At-speed" Logic BIST; and Scan-based diagnosis. To register, please contact Marc Brodnansky at brodnansky@syntest.com or call 310-265-1304
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