Flexible DSP Solution Key to High Speed WLAN Growth
With the introduction of 802.11 applications, operating in the uncluttered 5 GHz range and delivering data rates of 54 mbps, performance improvements have opened broader opportunities to designers.By Systemonic Corporation
High Speed Wireless Local Area Networks are fast emerging as the next major growth area in the wireless communications field. With improvements in performance and speed driven by new standards, wireless is becoming indispensable to a wide range of applications requiring flexibility and real-time updates, regardless of location. Add the promise of cheap and easy deployment and it's easy to see why companies have begun to consider the wireless option as part of their mainstream business operations.
Figure 1. Platform based partitioning approach
The first evidence of this development emerged in the form of 802.11b based Wireless LAN applications, operating at 2.4 GHz and allowing a shared maximum data rate of up to 11 mbps. In spite of limitations imposed by frequency crowding, this development got people thinking about the possibilities that wireless networks could bring to the table. With the introduction of high speed 802.11 applications, operating in the uncluttered 5 GHz range and delivering data rates of 54 mbps, performance improvements have opened broader opportunities, and more improvements are on the way.
Driving the process has been the performance of a new generation of high speed RF radio chipsets, which serve as the interface between the radio's RF signal and digital network access points. The chipset is an integration of technologies connecting an analog front end, used to transmit and receive RF signals, with a digital baseband module that processes the signal into a digital data format. Typical network hosts can include a laptop computer, desktop computer, Portable Digital Assistant (PDA), or a portal into a wired network such as Ethernet.
Figure 2. Code Generation Diagram, Tondelayo Baseband
Need for Multi Protocol Flexibility
Ironically, while the growing level of WLAN acceptance has boosted the prospects of wireless companies across the industry, it has also been a source of frustration. With technical and design issues still being resolved, prospective buyers have been reluctant to make commitments, preferring to wait for the deployment of standards that promise an even greater robustness to network performance. The only alternative has been to accept a chipset that may have to be replaced in the short run or modified at additional cost.
The root of the problem, at least until now, has been an inability to seamlessly upgrade fast breaking improvements quickly and at minimum cost. Unfortunately, most chipset designs lack the flexibility to accommodate new standards without a costly, time consuming retrofit process. The reason lies primarily in the fact that earlier baseband chips have traditionally been hardwired to meet a standard of choice and, as such, cannot be easily reconfigured.
In response to this problem, Systemonic has designed a groundbreaking feature into its new Tondelayo 5 GHz chipset that employs a software based solution to allow selection of new protocol solutions by a simple on board adjustment. In addition to providing for future standards, this capability is backwards compatible with existing standards as well. Since there are no hardware adjustments, service providers can implement the radio into their plans confident that future upgrades can be handled without interruption. Tondelayo also power provides signal levels and frequencies that are compatible with existing 802.11b power amplifier and low noise amplifier components for backward compatibility.
Tondelayo DSP Solution
Tondelayo is a fully integrated RF chipset based on the IEEE 802.11(a) standard for high-speed wireless networks in the 5 GHz UNII bands. The chipset includes a full solution RF front end integrated with a multi protocol baseband chip using C-OFDM modulation and best in class technologies in a flexible low risk design approach. Also included are CardBus and PCI reference designs and a robust suite of drivers.
Figure 3. Tondelayo DSP Core, Block Diagram
Because Tondelayo was designed as an integrated system from concept to solution, all the components are designed to work together in near seamless fashion. At the heart of the chipset's multi standard flexibility is a baseband chip which, unlike conventional baseband chips, uses a software-based multi protocol DSP solution to implement most RF waveform processing algorithms. Generated from a configurable platform, the DSP deploys the rapid generation of parallel DSP's and their accompanying tools, as required by standard selection.
During chipset operation, the baseband chip transforms the radio signal from a waveform to packet buffer contents on the host side. Using an 802.11a waveform as an example, this transformation is performed in several stages. First, a digital input filter rejects adjacent channels, and provides in phase and quadrature demodulation together with a suitable decimation of the input signal data rate. The processing then removes the guard interval between symbols and performs the Inverse Fast Fourier Transform (IFFT), prior to deinterleaving and depuncturing the symbols. The symbols are then decoding using a convolutional code and copied to the host memory. The host is then notified that a new packet is available.
For implementation efficiency, certain elements such as input filtering, scrambling/descrambling, encoding/decoding, interleaving/deinterleaving and puncturing/depuncturing are implemented with fixed function hardware that has some programmability via the selection of parameters. This allows the hardware to comply with different standards while maintaining a design that is efficient in terms of both space and power. Another efficiency is gained by running the time critical portions of the Media Access Control (MAC) firmware and the sequential control code for the waveform algorithms on the DSP, instead of using a separate processor.
The General Data Unit, shown in Figure 3, processes sequential control code and time critical MAC code at the same time that the eight Data Paths (DP) handle vector processing. The host processes higher level MAC functions that are not time critical. The use of a programmable DSP for waveform processing, along with programmable filters and other elements, has demonstrated initial success of a baseband chip designed to meet the 802.11a standard. It has also allowed the same chip to be used to meet the HiperLAN/2 standard merely through software changes.
Figure 4. Tondelayo Baseband Functional Diagram
In order to accommodate users who are considering or who have already committed to an 802.11a capability, Tondelayo provides a backward compatible option, requiring only minor adjustment to the baseband and radio. The same configuration can also be used to support 802.11g. Systemonic has already announced an 802.11a cardbus reference design. A unique product concept, Detect and Connect, has also been announced, which combines 802.11a and 802.11b into a single cardbus reference design. This allows a gradual upgrade of a wireless local area network from the 11 Mbps 802.11b standard to the 5 4Mbps 802.11a standard. As new standards come on line in the next couple of years this flexible, programmable architecture will allow implementation of the baseband waveform and data processing of the new standards using the existing baseband chip.
Conformance with 802.11 Standards
To achieve maximum efficiency, both the analog and the digital segments of the chipset must perform their respective functions in an optimum manner. In addition, they must work together effectively as an overall system. The need for such a high degree of seamless performance is driven by the complexity of the standards that have made 5 GHz high speed transmission possible. When the FCC allocated higher, uncluttered frequencies to wireless applications, it freed network designers from the restrictions of the crowded 2.4 GHz band and made uncluttered higher frequencies available. This decision afforded the bandwidth and modulation needed to permit operation at 54 Mbps, up from 11 Mbps in the 2.4 GHz band, which is well below the current norms for wired networks.
The FCC move also ushered in new regulations in the form of IEEE 802.11a and the European Telecom Standards Institute's Hiperlan/2, both of which were written to standardize performance criteria at higher frequencies. These criteria are based on the more complicated modulation schemes that higher frequencies require, adding further complexity to system development. This complexity makes it necessary for wireless radio designers to pursue a component strategy that will meet far more stringent requirements.
Both sets of standards utilize a unique and spectrally efficient modulation scheme known as Orthogonal Frequency Division Multiplexing (OFDM). OFDM is essentially a series of orthogonally separated subcarriers, each with its own modulated waveform. While the waveform properties are very well suited to an indoor environment, their implementation presents some unique challenges to system designers. Included among these challenges are accommodation of an inherently high peak-to-average power ratio, sensitivity to non-linearities of the analog components (i.e., gain compression and AM to PM conversion), and sensitivity to phase noise. A system designed without the appropriate amount of margin in any of these categories will generate an unacceptable level of bit error rates.
During chipset performance, the analog function is responsible for providing the amplification necessary to drive the antenna on transmit and the baseband A/D converter(s) on receive. It also must provide frequency translation(s) from the baseband waveform frequency to the UNII band. Additionally, in a waveform as complex as the multicarrier 64-QAM used in 802.11a and HiperLAN/2, it must provide sufficiently linear operation, utilizing close to the full scale range of the power amplifier on transmit and the A/D converter(s) on receive.
Figure 5. Tondelayo Baseband/RF Interface, Block Diagram
This requires a high degree of rejection of adjacent channels and out of band signals. Two approaches are used in current 802.11a offerings. One is the superheterodyne architecture, which spreads the channel filtering among multiple stages. The other is the zero or near-zero IF design. The tradeoff here is between more components that require less linearity in the superheterodyne case while providing higher performance, or fewer components that have very stringent linearity and filter cutoff characteristics in the zero or near-zero IF case that give less performance but have the benefit of lower component count.
Front End Performance
In an efficient RF front end, the ability to satisfy the necessary standards criteria is based on the performance of three units: the power amplifier, the LNA and the IF converter. Of the three, performance of the power amp is critical for two reasons, first because it literally controls the quality of the signal presented to the baseband at the other end of the wireless link, and secondly as the primary consumer of power, it must operate as efficiently as possible.
The Tondelayo power amplifier is part of an integrated front end, which also includes an RF up/down converter and an IF converter. The amplifier is developed in a proprietary 0.5 mm GaAs PHEMT process, affording high output power, low noise and excellent linearity. Systemonic's integrated implementation features transmit/receive and antenna diversity selection switches in addition to the amplifier gain stages, providing for lower loss, a better noise figure and reduced parts count. The amplifier provides designers with the ability to generate the maximum allowable output power for indoor applications in the 5.15 - 5.25 GHz band, while also covering all three UNII bands.
An important part of the amplifier's design includes features that have been built in not only for functional purposes but also for flexibility and simplicity at the network design level. For example, in addition to helping achieve better system noise figures, the module's integrated switches reduce parts count, cost and complexity. Internal matching of the RF impedances to 50 ohms, meanwhile, removes the need for added design work and complexity. Process tolerant active bias eliminates external bias adjustment, also for greater simplicity. Reducing quiescent current in the receive mode helps to extend battery charge time.
The RF and IF chips of the Tondelayo chipset implement a dual-conversion superheterodyne architecture for higher performance. They provide gain, gain control, and mixing functions at both the 5 GHz and 2.4 - 2.5 GHz bands. Both chips are built using Silicon-Germanium technology for best of breed performance, providing low noise and efficient power handling in a proven technology. The implementation provides a flexible frequency plan based on off-chip frequency synthesis using low-cost, commercially available parts.