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Chartered and Cadence Partner to Reduce Time-to-Market with Process Design Kit Offering; Companies Launch PDK Offering with Worldwide Seminar Series

Mon, 04/22/2002 - 12:40pm
Cadence Design Systems, Inc. (NYSE:CDN) and Chartered Semiconductor Manufacturing (Nasdaq:CHRT)(SGX-ST: CHARTERED) are working together to help the mixed-signal market reduce cycle times on designs with new Chartered foundry process design kits (PDKs). The PDKs will integrate Chartered's manufacturing processes for multiple nodes — from 0.35 micron extending to 0.10 micron — with the Cadence(R) front-to-back design and verification flow for analog, RF and mixed-signal ICs. The result is a design-through-manufacture path that helps companies meet aggressive product schedules for advanced mixed-signal SoCs.

To introduce the PDKs to the market, Chartered, one of the world's top three foundries, and Cadence, the world's leading supplier of electronic design products and services, will co-host a worldwide seminar series, Acceleration to Technology Access, at the following locations and dates: San Jose, May 7; Irvine, Calif., May 9; Boston, May 14; and Austin, May 16. Locations and dates for international seminars will be announced at a later time. Additional information and online registration is currently available at http://www.charteredsemi.com/PDK.htm.

The PDKs will enable Chartered and Cadence customers to immediately begin designing chips rather than first developing their own required process design kits. The PDKs provide a symbol library and technology file for the design automation flow and DRC-correct parameterized cells to automate device generation. They are validated with the Cadence Spectre(R) models in the Cadence RF/analog mixed-signal design solution, which includes AMS Designer, Composer, Analog Design Environment, Spectre/Spectre-RF, Virtuoso(R) Layout Editor and XL, Custom Placer, Custom Router, and the Assura(TM)/Diva(R) physical verification suites.

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