Product Releases

Boundary Scan Test and In-System Programming Environment

Fri, 03/08/2002 - 3:55am
A new release of ASSET InterTech's ScanWorks boundary-scan (IEEE 1149.1/JTAG) test and in-system programming (ISP) environment features next-generation interconnect test tools that improve product quality by offering better test coverage and by speeding up the test development process with new simpler test development capabilities. The ScanWorks system also has seamless integration with Agilent Technology's 3070 in-circuit test systems, offering test and programming algorithm re-use from prototype design through volume manufacturing.

The new version of the ScanWorks system (Version 3.2) includes a capability known as cluster modeling which is able to more completely describe PCBs with non-boundary-scan devices and thereby provide better boundary-scan test coverage. By increasing the speed of the ScanWorks software through algorithmic and database improvements, users can now generate boundary-scan tests in as little as 20 percent of the time required previously. With today's complex circuit boards, many of which can contain as many as 10,000 device nets, reducing the time to generate a test can have a major effect on the overall test development process. The new ScanWorks system also includes a node browser that provides intuitive and interactive access to the PCB to enable simpler and faster development of tests that will be safe for the circuits on the board.

With Version 3.2, the ScanWorks system's integrated design browser has been improved with new features for sharing layout and schematic data. The integrated design browser generates a view of the board-under-test based on information from electronic design automation (EDA) systems. A design browser interface allows designers and test engineers to correlate boundary-scan test information and design data within the ScanWorks environment. Test engineers or technicians do not need access to the EDA system to take advantage of the schematic and layout information that was used to generate a design.

In addition to providing layout and schematic views of the design, the new ScanWorks system can extract device type and interconnect data directly from the EDA files that were used to build the PCB. This information is used by the ScanWorks system to produce netlists to generate the test patterns for the board. In the event that design data is not available, traditional netlist information can be imported into ScanWorks using any popular format, such as Allegro, Cadence/Concept or Mentor Neutral.


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