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Synchronous Pipeline Burst SRAM

Tue, 10/30/2001 - 8:03am
White Electronic Designs Corporation announces a 256 K × 72 Synchronous Pipeline Burst SRAM, single-cycle deselect (SCD). The WEDPY256K72V-XBX is a high performance SSRAM with a 2-bit burst counter. It is designed to provide L2 secondary cache for high-performance CPUs, with Linear or Interleaved Burst sequence. The high performance access rate is 3-1-1-1.

The WEDPY256K72V-XBX operates on a 3.3 V power supply. All inputs/outputs are 2.5 V, using a separate I/O power supply. The SSRAM is designed for a 64-bit data bus, and contains 8 bit of parity. The PBGA has multiple VCC and VSS pins, and three chip selects for simple depth expansion. For portable applications, an automatic power-down mode is available. WEDPY256K72V-XBX is packaged in 159-bump PBGA, plastic ball grid array, 14 mm × 22 mm, to provide 16 Mbit of high performance secondary cache.

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