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PCI Backplanes

Fri, 09/28/2001 - 9:40am
Tracewell Systems announces the availability of two CompactPCI backplane series for industrial, data and telecommunication applications. The cPCI and H.110 Telecom backplanes combine standard architecture and high-frequency telecommunications designs for 6U board heights and are available for various slot sizes.

Tracewell Systems cPCI backplanes provide a 64-bit CompactPCI bus that is fully compliant with PICMG 2.0-R2.1, including hot swap capability and slot geographic addressing. The 8-layer all-stripline design used an SMT/press-fit construction that is optimized for signal and power distribution and uniform impedance. A right-justified system slot is available allowing use of all slots, even with multi-slot CPU boards. Left-justified versions also are available. Power terminals are positioned adjacent to the system slot to provide more efficient power distribution and wiring. This orientation allows a 6U overall board height while providing full access for rear plugging boards. Power connections utilize a combination of ATX and high current power taps to support a wide range of power harness configurations.

A 14-posistion system header also provides access to PRST#, DEG#, FAL# signals, as well as logic return and remote sense. Matched clock lines minimize skew while ground guarding reduces line-to-line crosstalk. Universal I/O for +3.3 V or +5.0 V is provided, along with a frame ground bus. To help eliminate the problem of bent pins during installation of rear plugging I/O boards, 'AB' type connector shrouds are installed on both P3 and P5 in all slots. Other conveniences include two auxiliary power connectors for peripherals.

Tracewell Systems H.110 backplane was designed for high performance telecommunication applications. The H.110 and cPCI backplanes are similar, but the H.110 Telecom Backplanes combine a 32/64 compatible CompactPCI bus with an embedded TDM bus. Also, the H.110 utilizes a 10-layer board design. The P4 H.110 TDM bus extends to all slots, except the system slot, allowing CPU feed-through I/O and segment bridging.

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