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Timing Analyzer

Mon, 07/16/2001 - 5:48am
Incentia Design Systems announced its first product — TimeCraft™. TimeCraft is a full-chip gate-level static timing analyzer for timing sign-off. It offers fast run time speed and accurate timing analysis results for high performance deep sub-micron (DSM) system-on-chip (SoC) designs with multi-million gates.

TimeCraft's timing engine is tightly integrated with Incentia's new synthesis products that will be announced soon later this year. It allows designers to use the same timing engine throughout the design, synthesis and tape-out processes for more consistent timing results and more complete comprehension of all timing constraints. Benchmarks confirm that for large designs with complex timing exceptions, TimeCraft runs 15 times on average faster than competing tools.

TimeCraft supports the full set of Synopsys Design Constraints (SDC). It offers unique features and many advanced options beyond the full set of SDC scope. For example, in addition to the regular "time borrowing mode", TimeCraft provides a more intuitive way to analyze timing in latch-based designs and un-clocked registers using the so-called "pass-through mode."

Today's synthesis solutions perform simultaneous logic and physical optimization to achieve timing convergence. While this approach is adequate, the process can be further improved for multi-million-gate DSM SoC designs with complex timing constraints.

Due to run time and capacity limitations, existing synthesis solutions either use different timing engines or can only consider a portion of the timing constraints between the synthesis and the sign-off stages. This timing inconsistency introduces problems in timing convergence and performance results. Incentia's solution is to use a single timing engine that is highly efficient to handle the same set of complex timing constraints at both synthesis and sign-off stages.

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