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Design Planning Products

Mon, 07/16/2001 - 5:44am
Tera Systems announced a major upgrade to its TeraForm® RTL design planning solution, TeraForm 2001.1. Enhancements to the TeraForm analysis partitioning, floorplanning and timing-optimization capabilities solidify the product's status as the new front-end to today's gate-level, logic synthesis and layout solutions for high-performance system-on-chip (SOC) design.

TeraForm is the first tool of its kind to give chip designers essential visibility and control over their chip's logical, physical and timing domains well ahead of gate-level synthesis and layout. Unlike other EDA approaches that require logic designers to learn how to do physical layout, TeraForm enables logic designers to focus on register-transfer level (RTL) design creation and optimization and then to hand-off a superior design to the physical implementation team. By producing a better starting point for existing gate-level synthesis and layout tools, TeraForm enables faster downstream design convergence with fewer iterations late in the design cycle.

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