The PSI2G100S integrates a SONET/SDH OC-48 (2.5 Gbps) transceiver, clock data recovery (CDR) circuitry, a SERDES, 100k gates of programmable logic, and 240 Kbits of communications memory, targeting OC-48/STM-12 optical terminators, SONET/SDH routers and add-drop MUX subsystems.
The PSI2G100S closely follows the introduction of the PSI2G100, the world's first 2.5 Gbps programmable PHY. PSI devices offer operating speeds from 1 × 2.5 Gbps to 8 × 1.5 Gbps to support high-bandwidth applications.
PSI devices combine the flexibility, predictable timing, and ease-of-use of Cypress CPLDs with a SERDES, communications memory and phase-locked loops (PLLs). Cypress's Warp(TM) R6.1 software enables a seamless programming interface to allow design engineers to easily integrate custom IP with the SERDES via HDL blocks, HDL text, or graphical state machines. Cypress is the only company to offer a SONET/SDH OC-48 compliant, 2.5 Gbps SERDES, programmable logic gates, design entry, synthesis and verification in an integrated, single-chip solution.
The PSI2G100S is perfectly suited for both port and backplane solutions in a typical line card application. Its programmability enables customers to create customized and flexible solutions for the parallel-side interface for example, taking an OC-48 data stream from the serial side and converting it to a 32- or 64-bit parallel-bus topology on the other.
The devices in the PSI family provide a programmable interface to a SERDES that is compatible with various physical layer transmission media -- fiber optic modules, copper cables and circuit board traces. Along with optimized communications memory (such as dual-ported and FIFO memories), logic and PLLs, the ICs will provide parallel programmable I/Os supporting LVCMOS, LVTTL, 3.3 Volt PCI, SSTL2, SSTL3, HSTL, and GTL+ inputs. The combined serial bandwidth of 200 Mbps to 12 Gbps will allow PSI devices to meet the requirements of a broad range of market segments.