Based on the 256-ball, fine-pitch ball grid array (FG256) package, the board is available with the 40,000 gate XC2V40 or the one-million gate XC2V1000 device. The board provides a JTAG connector for direct configuration of the Virtex-II FPGA as well as an XC18V series in-system programmable configuration memory (ISP PROM). Multiple clock domains are implemented with the two onboard 100 MHz and 24 MHz oscillators and two external clock input connectors.
User-selectable bank voltage and reference voltage jumpers support many SystemIO standards and let the user configure each bank of I/O pins to operate in 1.5 V, 1.8 V, 2.5 V or 3.3 V mode. Five of the eight I/O banks contain high precision VRN and VPN resistors that support the Virtex-II architecture's digitally controlled impedance (DCI) capabilities. A sixth bank contains two potentiometers for the VRN and VPN inputs, giving the bank a 24-525 Ohm range. The flexibility of these settings and configurations gives designers numerous options for exploring the many features of the Virtex-II I/O.