Lattice Semiconductor introduces the first two members of its new MachXO family. Through the use of 130 nm non-volatile embedded Flash process technology, and the use of an industry-standard 4-input Look-up Table (LUT) approach for logic implementation, the MachX0256 and MachX0640 provide system designers with up to 50% lower cost per logic function. Lattice has added to all family members distributed memory and the ability to transparently update logic configurations through the company’s TransFR technology. In addition, support for Embedded Block RAM (EBR) and phase-locked loop (PLL) clock circuitry, as well as PCI and LVDS I/O, has been added to the larger family members. The MachXO logic devices are built on a 130 nm embedded Flash process technology that enables instant-on operation in a single chip. Pin-to-pin delays as fast as 3.5 ns allow the devices to address the high-speed requirements of contemporary system designs. MachXO devices are suitable for the implementation of a wide array of functions, including bus bridging, interfacing, control logic, clock management, power and reset control, glue logic, memory control and ASIC and FPGA configuration.
Lattice Semiconductor Corporation