CellularRAM memory is an ideal companion volatile memory device to high speed burst Flash.
By Odilio Vargas, Micron Technology, Inc.
Handset designs are at the forefront of IC technology, in both digital baseband and memory. New wireless handsets require a unique combination of performance, low power, low cost, and adequate manufacturing volumes. Micron is at the forefront as well, developing memory architectures meeting this market's growing demands with a cutting-edge companion device to high-speed burst Flash called CellularRAM memory.
Emerging wireless standards, like 2.5G and 3G, allow for faster data rates across an air interface, thus enabling a new set of application programs including MP3 players, multimedia messaging, sophisticated organizers, and video streaming to operate on handsets. However, these new requirements expose the limitations of earlier memory architectures, like low-power Flash and SRAM, in wireless handset designs. Traditional asynchronous access mode, the workhorse memory interface of handsets, can no longer cope with increased demand for bandwidth. Even the most recent page mode access is already showing limitations.
Adding a burst protocol to a Flash memory device is the best solution for delivering high throughput while maintaining efficient power consumption in wireless handsets. The new generation of memory controller cores and DSPs can cache both instructions and data for faster execution. This makes burst-capable memory even more attractive, since the entire instruction cache can be quickly filled by a single burst read from the memory. A burst protocol can also fill and flush the data cache more efficiently, enabling fast context switching. All these advantages illustrate why the burst protocol has become the de facto interface for wireless Flash devices. In addition to Micron's 1.8 V burst Flash, other compatible burst products include the Intel® W18 wireless Flash and K3/K18 StrataFlash and STMicroelectronics' M58WR product family.
While memory manufacturers quickly developed innovative, higher-bandwidth Flash, their response has been slower with low-power SRAM. Page mode access, initially applied to 6T low power SRAM, is the most significant improvement toward higher throughput in wireless platforms. Although this approach has improved the situation, it still does not allow memory controllers to benefit fully from the newest burst mode Flash interface. Even newer Pseudo SRAM product offerings demonstrated a slow evolution to higher throughput using page mode access. System designers, therefore, are faced with a situation where two different memory devices operating on the same bus cannot function efficiently together. These challenges are what drove Micron, Cypress, and Infineon, to develop a solution.
A Multi-Generational Family of Low Power PSRAM
CellularRAM memory is our answer to handset designers' demands for a faster, more efficient, and simpler design in a high-throughput memory subsystem (Figure 1).
Figure 1. Advanced 2.5G Handset Architecture. [Note *Off-board data storage in the form of card (i.e., MMC, SD or Memory Stick)]
CellularRAM memory supports a burst protocol that is fully compatible with low-power Flash, making the memory controller design much simpler and more straightforward. It also leverages JEDEC-standard, advanced power management enhancements for Mobile SDRAM, designed to reduce active and standby current levels. Micron improved upon burst Flash operation by incorporating an innovative burst write capability that permits the same data rates into and out of the CellularRAM device. This combination of feature sets makes CellularRAM memory a useful data-storage device for storing and executing code.
The key features of burst-capable CellularRAM memory include:
Compatible burst protocol with standard burst Flash
Similar access time of 60 ns
Max burst clock rate of 108 MHz
1.8 V I/O and core power supply
Low active (35 mA) and standby (80 mA) power
Innovative burst write capability
Enhanced, advanced power management features; JEDEC Mobile SDRAM-compatible
Unlike the PC industry, wireless platform requirements vary considerably from one wireless standard to another leading to a variety of possible memory subsystems. Figure 1 shows an advanced 2.5G cellular phone with a unified memory bus between a wide range of memory interfaces (i.e. Asynchronous, Page, or Burst bus). This leads to specific memory subsystems addressing precise data throughput in relationship to clock frequency and power consumption. The combination of CellularRAM memory and burst Flash is able to balance all three factors to satisfy advanced 2.5G and entry-level 3G wireless standards.
Providing Performance, Power, and Price to the Handset Market
By assigning specific tasks to the memory subsystem, a wireless chipset is able to utilize a bus and reduce the possibility of bus contention. This is aided by a trend in wireless chipset manufacturers to introduce dual processing capability in one chipset, for example a modem and application specific core, for future 2.5G platforms. Dual processor architectures will store executable code and some data in burst Flash while only data storage is done in CellularRAM memory. This is similar to the popular 2G approach with an Asynchronous interface for both the Flash and SRAM devices.
But as the chipset increases frequency, the ability to reduce wait states within asynchronous memory devices is no longer possible and must transition to a burst interface to improve data throughput on a unified memory bus. The memory subsystem analysis (Figure 2) demonstrates how an asynchronous-only interface will have a bottleneck of less than 50 MB/s. By not reaching 50 MB/s, an Asynchronous interface is no longer able to handle the increased bandwidth necessary for a 2.5G wireless standard.
Figure 2. Memory Subsystem Analysis. (Notes: 1. Profile assumes a 90% sleep - 6% idle - 4% operating mode. 2. System memory activity hypothesis: 70% - code fetch access and 30% - data accesses (70% read and 30% write) 3. 16bit data bus width.)
But a Burst Flash and CellularRAM combination device can allow 116 MB/s with a 66 MHz bus frequency and increase almost 30% to 165 MB/s when moving a burst bus to 108 MHz.
By penetrating the 150 MB/s data throughput barrier, the burst Flash and CellularRAM combination device is then able to address the needs of an entry-level 3G wireless platform. Combined with CellularRAM memory's low active and standby currents of 35 mA and 80 mA, respectively, a burst Flash and CellularRAM device offers wireless designers an appealing low power consumption of 1.4 mW.
Transitioning a unified memory bus with an SDRAM interface would be the next evolutionary step after a burst Flash interface. Although this new bus can significantly increase data throughput, it comes at the expense of power consumption. A wireless designer will then have to evaluate the trade-offs between a memory usage model leveraging a burst Flash and an SDRAM interface. Figure 2 shows that moving to an SDRAM interface with a SyncFlash® memory and Mobile SDRAM will generate a boost in data throughput to 197 MB/s, an increase of 15% over burst Flash and CellularRAM memory but at the cost of x2 the power consumption to 3.0 mW.
Rather than attempting to use a single unified memory bus, many 3G + phones will require the need for multiple memory buses to co-exist in order to effectively balance bandwidth, power consumption and cost. Until then, a unified memory bus will be attractive for advanced 2.5G and entry-level 3G phones by leveraging a burst mode Flash and CellularRAM devices.
The CellularRAM product family offers high-performance handset designers a unique combination of performance and power efficiency in a simple, straightforward design. It is an ideal volatile memory companion to the popular burst Flash memory.
For more information on CellularRAM memory, visit www.cellularram.com. For more information on Flash devices, visit www.micron.com/flash.