Design Tool Suite Supports Efficient FPGA Design
Lattice Semiconductor Corporation announces Version 7.2 of its ispLEVER FPGA design tool suite with advanced place-and-route algorithms that deliver high performance results in 30% less time. The ispLEVER 7.2 software also supports proprietary "clock boosting" flow for the LatticeECP2 and LatticeECP2M FPGA families. Clock boosting can result in up to a 5% increase in FMax with no additional user input. In addition to performance improvements, ispLEVER Version 7.2 improves productivity with additional control, analysis and workflow enhancements, and it includes the latest release of Synopsys' Synplify Pro advanced FPGA synthesis solution. This software can analyze a design and automatically choose the most appropriate algorithm for the design's topology. The Trace static timing analysis report includes a "clock domain analysis" section.