Glossary of AcronymsADC — Analog-to-Digital Converter 3GPP — 3rd Generation Partnership Project
ASP — Application Service Provider
ASIC — Application-Specific Integrated Circuit
NOC — Network Operations Center
SDR — Software-Defined Radio
TEM — Telecom Equipment Manufacturer
CDMA — Code-Division Multiple Access
GSM — Global System for Mobile Communications
FPGA — Field-programmable Gate Array
W-CDMA — Wide-CDMA
TDM — Time-Division Multiplexing
ATM — Asynchronous Transfer Mode
BOM — Bill of Materials
BTS — Basestation
HSDPA — High Speed Data Packet Access
IP — Internet Protocol
LIU — LAN Interface Unit
MAC — Media Access Control
NBAP — Node B Application Part
NPU — Numeric Processing Unit
OFDM — Orthogonal Frequency-Division Multiplexing
PPP — Point-to-Point Protocol
RAN — Radio Area Network
ROI — Return On Investment
SNMP — Simple Network Management Protocol
UMTS — Universal Mobile Telecommunications System
Basestation developers are, now more than ever, looking for more cost-effective ways to maximize subsystem design reuse, reduce design complexity across product families and future-proof designs. NPUs are a key element is this strategy.
By René Torres
Over the last five years increasing cost pressure on BTS hardware development has been unremitting. During this period the average selling prices of some basestations have declined by as much as 50 to75%. Increasing competitive pressure from new BTS manufacturers in Asia has led many designers to look at lowering system costs in multiple ways. One of these strategies includes minimizing out-of-ycle board spins, where possible, from incremental feature introductions such as new protocol changes.
Mitigating Design Cost Risk with Network Processors
At the heart of this challenge for designers is the balance of accommodating multiple evolving wireless standards, while minimizing hardware design churn, and maximizing ROI on scalable system design. Within the UMTS market for example, before 3GPP released the R5 specification, ATM was the leading protocol for transport. Shortly afterward in 2001, the cost advantages of using IP led to the evolution and development of the IP RAN standard with Point-to-Point Protocol. In parallel, the basestation's baseband architecture has continued to evolve to deliver an increasing number of radio standards such as the R5, R7 specifications (HSDPA, HSUPA) as well as OFDM. This challenge, coupled with increasing ASP pressure on manufacturers to reduce cost of goods sold and accelerate time to market, has lead to increasing interest in adopting COTS solutions such as NPUs.
Traditional BTS designs with ASICs, for example, can often require 18 months or more of development time, as well as a significant initial outlay of money for design, mask and start-up fabrication. However, if networking protocol standards were to change after the initial ASIC design, the developer would then need to modify and re-spin the ASIC. Although it's very common that the second generation ASIC's development time is significantly less due to architecture reuse (e.g. nine versus 18 months), the designer will still often need to redesign and manufacture a new card with the second generation ASIC. The end result from this approach can be very costly for the service provider, as they may have to prematurely upgrade their systems by replacing their existing card with the new one.
With an NPU-based solution designers can eliminate several of these challenges. Because NPUs are sold OTS and often bundled with pre-validated application software, the NPU solution can cost significantly less in terms of development time, engineering manpower and up-front cash flow investment. NPU designs, on average, typically take less than 12 months to develop. In addition, the NPU can potentially eliminate the need for introducing new silicon and board spins for out-of-cycle changes. The reprogrammability of the NPU would enable the designer to implement the new protocol standard via separate software upgrades that are independent of the incumbent silicon. Under this scenario the designer can potentially rollout multiple future upgrades with minimal impact to existing product lines, which may already be installed at customer premises. This is particularly critical, given that many service providers are, more and more, requiring basestation solutions that can be upgraded remotely from the NOC through SDR solutions without the need for a manual truck roll.
Network Processors Deliver Reuse in Multiple Basestation Subsystems
TEMs today are also looking for ways to extend their investment in their NPU design across subsystems as well as product families. Legacy CDMA and GSM basestations, for instance, were often designed with proprietary ASICs and FPGAs. These ASICs and FPGAs were typically used for one specific subsystem component such as a line card or baseband channel card. Frequently, these subsystem designs were not scaleable and could not be reused in parallel sister basestation designs. Many developers now want to look at ways to design subsystem components with COTS silicon and software solutions that can be reused and refitted across all of their basestation designs to maximize the net present value of their hardware and software design investment. Several basestation TEMs today offer multiple basestation product lines based on each of the evolving or emerging radio standards (WCDMA, CDMA2000, TDSCDMA, as well as 802.16e WiMAX). These basestation product lines often offer multiple different line card transport implementations (TDM vs. ATM vs. IP). Whenever possible, TEMs are looking for the capability to develop all of their basestation product lines, regardless of flavor, under common hardware subsystem components and software architecture platforms.
For example, in a typical basestation based on the OBSAI system architecture model, there are four primary subsystem modules as shown in Figure 1: radio frequency module, control module, baseband module and transport module. Traditionally, basestation development has required the use of proprietary ASICs for both the baseband and transport module processing. This often requires a significant cash flow commitment and engineering resource investment on the part of the developer to define and support the validation of the ASIC from start to finish.
Today, network processors have evolved to offer developers a new scalable silicon solution that can be reused in the same basestation design through software defined programming to perform multiple different functions of a basestation system. For example, designers can actually reuse the same NPU for processing functions in the transport, baseband and control modules. This high level of reuse gives TEMs a significant commercial advantage over the use of legacy ASICs by enabling them to implement new protocol standards via software in each of the three modules as they continue to evolve, as well as reduce multi-vendor development complexity.
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Figure 1. Four Basic Building Blocks of a Basestation.
Figure 2 provides an example of how an NPU can be used to develop a 3G basestation line card using a commercial off the shelf software application kit to implement multiple transport protocol standards. Under this usage model, TEMs could develop their line card with the NPU to perform ATM RAN line termination based on an AAL2 or AAL5 software kit implementation. The developer can then take that same card design and differentiate it via a separate IP RAN software kit to support PPP, ML-PPP, and MC-PPP processing. Each of these line card implementations can then be fitted to interconnect to either a layer 1 T1/E1 LIU, or OC3 PHY interface standard to address different market requirements as needed.
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Figure 2. Example of 3G Basestation Line Card Design.
Historically, NPUs started out in the wireless design world as competitive replacement solutions for ASICs and FPGAs in next generation line card designs. However, as basestation architectures have continued to adopt more OTS component solutions, NPU solutions have likewise continued to evolve to be able to service more value-added functionality in the basestation. Figure 3 shows how the same NPU used in the previous line card example can be reused to perform Layer 2 MAC processing in a modem baseband card for new emerging radio standards such as 802.16e Wi-MAX. In this usage model, the four microengines (MEv2) of the network processor can be programmed and partitioned by commercial software tools and development kits to process the subset protocols of the MAC layer while the low power integrated processor core can process the channel card's complicated uplink/downlink scheduling in parallel.
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Figure 3. WiMAX Baseband/LIU Card
NPUs Offer Increased Value through Integrated Features
In addition to supporting multiple subsystem roles and processing requirements (transport, baseband, etc.), many NPUs offer basestation developers rich value-added features. For example, in Figure 4, the network processor includes an integrated security engine and high performance control plane processor. The integrated processor core in this NPU can potentially be partitioned separately under software to perform NBAP control plane signaling and or SNMP system management processing, thereby potentially reducing the need to design a control module with a separate dedicated CPU. These value-added features allow TEMs to further increase their investment by consolidating a significant number of mission-critical functions on one strategic processor platform, minimizing their design's BOM cost as well as reducing board layout design and validation complexity.
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Figure 4. Integrated Features of the Intel® IXP2350 Network Processor.
NPUs Consolidate Development Environments
Each of the four basic basestation subsystem modules is continuing to evolve by adapting new protocol standards and specifications from the 3GPP standards body. These future adaptations can potentially drive significant incremental cost and churn throughout the lifetime of a basestation product line. NPUs, however, are inherently designed to provide system developers with a flexible software-defined architecture that helps future-proof hardware designs against changing standards. Designers implement the majority of these adaptations by reprogramming the silicon via software instead of respinning an ASIC or the entire card.
Figure 5 illustrates how a traditional ASIC-based basestation design could potentially require up to three different software development environments with two or more independent software engineering teams. In contrast, an NPU-based design offers a centralized software development environment based on one family of compiler tools and development kits. A common software development environment can often provide time and cost savings for developers by minimizing intra-design team complexity. Furthermore, many NPU manufacturers offer a common set of software tools and development kits for all of their NPU product lines. Because of this, much of the NPU software learning curve gained from a centralized BTS software team can often be scaled over to other peer wireless designs, outside of the basestation product line, that may also be designing with the same NPU architecture (e.g., RNC or BSC).
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Figure 5. Maximizing Software Reuse with Common Platforms.
Scaling an NPU Investment Vertically & Horizontally
As NPUs continue to increase in performance and provide richer integrated features over their ASIC counterparts, basestation developers are continuing to look at how they can maximize their investment in them as a strategic common platform. As shown in Figure 6, this reuse opportunity starts at the basic subsystem level. Developers can begin to maximize economies of scale at a vertical level by reusing a strategic NPU across the transport, baseband and control modules of their basestation design as appropriate. Over time, this initial investment can provide a common platform architecture blueprint at a greater system level that can be further shared and adapted on a horizontal basis to reuse across multiple basestation product lines. NPU adoption and reuse at the vertical and horizontal level is becoming increasingly important to the bottom line as basestation manufacturers continue to look for ways to reduce design cycle complexity and maximize their investments across multiple BTS product families.
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Figure 6. Maximizing NPU Common Platform across BTS Product Lines and BTS Function.
Today's NPUs offer basestation developers several compelling advantages over developing with traditional ASICs that are driving increased adoption in the market. Included are:
1. Faster time to market via standard OTS offerings (both silicon and software).
2. Reduced development environment complexity under one silicon platform for three different subsystem functions.
3. Lower cost of goods sold:
NPU reuse in multiple BTS functions (horizontal)
NPU reuse in multiple BTS product lines (vertical)
Reduced system-level BOM costs
Reduced silicon vendor complexity, enabling economies of scale
NPUs will continue to provide developers with a strategic cost, development and market advantage for basestation subsystem designs of all flavors and functions. Like the wireless industry itself, NPUs are continuously evolving. NPUs will continue to advance to offer more highly-integrated, flexible solutions for developers to future-proof their design investments in an increasingly complex wireless market.
Intel and Intel XScale are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Copyright 2005 Intel Corporation. All rights reserved.