STMicroelectronics introduces the Turbo μPSD3300 series of its μPSD family of 8051-class embedded Flash microcontrollers. The Turbo μPSD3300 series increases performance to 10 MIPS peak and adds a peripheral set to form an SoC for embedded control applications. A few of the enhancements for the Turbo µPSD3300 series include a 16-bit programmable counter array (PCA), 10-bit resolution ADC channels, SPI and IrDA interfaces. ST's μPSD3300 devices feature dual independent banks of Flash memory, up to 32 Kbytes SRAM, and over 3000 gates of programmable logic with 16 macrocells. The dual bank Flash architecture and programmable decode logic support true READ-while-WRITE concurrent access, otherwise known as In-Application Programming (IAP). Memory mapping is handled by an integrated decoding PLD that can assign any Flash or SRAM memory segment to any address on any memory page, or bank. Flash memory can be allocated to 8032-code space or data space in almost any proportion as needed. Other peripherals include six PWM channels, an I2C master/slave bus controller, two standard UARTs, supervisory functions such as a watchdog timer and low-voltage detect, and up to 46 general-purpose I/O pins.
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