Programmable Clock Dividers
The SY89871/2/3/4/5/6 are precision 2.5 V and 3.3 V high speed LVPECL and LVDS programmable clock dividers. Whether the input signal is AC-coupled or DC-coupled, no external components are required in the signal path to interface with the family. Within-device skew is less than 15 ps; rise and fall times are less than 250 ps. The family features a total jitter of less than 10 ps(pk-pk) over temperature and voltage.
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