Phase Locked Loop
The SCG4521 model has a primary LVPECL OC-3 output and a secondary (OC1) CMOS reference output. Both outputs have a maximum 40/60 duty cycles and are phase locked to one of two selected input references. The SCG4521 phase locked loop relies on a fundamental frequency, low jitter, voltage controlled, crystal oscillator. They are ideal for SONET/SDH line cards in network element equipment operating from OC-1 to OC-48. Features included < 1 ps RMS jitter, < .2 dB phase gain, hitless reference switching and 20 ppm Free Run.