OEMs & Aftermarket Battery Packs
Aftermarket vendors may resort to practices that compromise the end user experience or safety to make battery packs inexpensive and attractive to the consumer.Jeffrey VanZwol, Micro Power Electronics
Battery Pack Safety FeaturesBattery packs are no longer a simple configuration of cells. They are carefully engineered products with many safety features. The main components of a battery pack include: the cells, which are the primary energy source, the printed circuit board, which provides the intelligence of the system with features such as the fuel gauge and protection circuitry, the plastic enclosure, external contacts, and insulation.
All packs should be designed to withstand a moderate amount of shock and vibration, but the requirements can be much greater for equipment used in the field instead of a home office. Seemingly random battery fires are often attributed to aftermarket or "fake" batteries. When overstressed, any Li-ion technology can be hazardous to a degree. Extra caution must be exercised during the design process to ensure that the cells are being utilized in a manner appropriate to the technology.
Growth in the Aftermarket EcosystemThe product life cycle of a portable device in the medical, commercial military and industrial equipment markets often exceeds the cycle life of the product's battery. The high price of medical, military and industrial devices, in combination with the increasing volumes of portable devices, opens our markets for third party replacement batteries. Aftermarket vendors may resort to activities that compromise the end user experience or safety to make the battery packs inexpensive and attractive to those purchasing replacement packs. Counterfeit products are found easily on the web for most portable products. In an analysis of aftermarket battery packs, compared with their counterparts from the original manufacturer, many quality issues were observed in the aftermarket battery packs.
Analysis of Counterfeit Battery Packs
Use of substandard or unqualified cells;
Mismatched components on circuit boards that may not provide adequate performance;
Lack of a current/voltage or thermal protection circuit;
Lack of accommodation for normal cell swelling over time;
Nonexistent or obstructed gas vents;
Bad welds or solder joints.
Figure 1 illustrates some of the poor manufacturing quality issues observed in a selection of counterfeit battery packs.
Bad welds are by far the most commonly observed problem, and they can serve as a warning signal. Figure 1 shows an example of problematic welds. Welds such as these should be caught in a next step inspection process and if they are present in a battery pack that goes out to the market, it is a strong indication that the manufacturer's quality processes are not sufficient.
A small amount of separation should be included in the form of a polymeric shock absorbing material between the cells. During periods of vibration or shock, the shrink wrap insulation around the cells can be damaged and expose the cells to an increased likelihood of shorting or mechanical damage. Figure 3 shows an aftermarket battery where the cells are not separated at all.
Any bare, loose conductor is a potential hazard and a sharp bare piece of metal is especially troublesome. In a properly manufactured battery, the Nickel strips should be separated and insulated to prevent shorts between strips and prevent cutting the insulation on the nearby wires. The strips in a counterfeit pack are completely bare. These strips are long and wrap around so the concern is increased. They could touch one another or cut into other insulation (see Figure 4.)
Protecting Your Products and Brand EquityIf you produce higher volume portable devices, it is your responsibility to protect your company from the aftermarket packs. One way to protect the end user and provide the best performance is to authenticate battery packs and other accessories. There are many options available to design in protection against aftermarket batteries.
The most obvious is the form of the packaging and connectors, but this approach can be circumvented by simple measurements, and once a counterfeit or clone is available the original manufacturer would have to change the form factor, a non-trivial task.
Labeling, such as stickers, certification markings, & holograms are another possibility, but good quality, cheap, scanners and color copiers make these methods easy to reproduce. Web based registration is another idea, but it creates an inconvenience for the user.
The design engineer's objective is to increase the pain level of an unauthorized manufacturer so that they choose not to manufacture a clone of the battery pack. An electronic challenge and response or electronic identification (ID) may be warranted for the protection of the OEM's product; the added cost of an ID based solution may be sufficient to achieve the goal of increasing the time and expense to create counterfeits.
However, a simple ID approach should not be considered secure because an oscilloscope measurement will give all the information needed to reproduce a static ID. If an unauthorized manufacturer is willing to add the cost to reproduce the ID, then this system fails to protect the end user or the OEM.
Increasing in complexity, a changing challenge and response between the battery and the device is a more secure approach. It requires a secret that is shared between the host and the battery, random input, and an algorithm for generating an output that is difficult to predict. Selection of the correct authentication technique is about understanding the tradeoffs to be made.
One strategy that an engineer could employ is the cyclical redundancy check (CRC). In this system the challenger, which is the host, sends a command to read the ID from the responder, which is the battery or peripheral. The data returned from the device includes the product family code, ID and CRC value. The CRC value is used to ensure that the data is transmitted completely and correctly. The host checks the validity of the data and determines how the system should react based on that validity. A more secure version of the Challenge/Response technique requires four things missing from the CRC approach:
A secret that is shared between the host and the peripheral;
A good random input;
An algorithm for generating an output that is difficult to predict based on the input and the secret;
The algorithm should not be easily analyzed such that the secret can be determined.
The algorithm itself does not need to be a secret. In fact, a public domain algorithm, such as a SHA-1/HMAC, is preferred because it has been reviewed by a large group of people that have determined that the secret cannot be deduced from the output. Fortunately, many of the latest gas gauges have SHA-1 based authentication as one of their features, so simply planning for the implementation of this feature with appropriate design on the host side is all that is necessary to implement a secure ID solution.
ConclusionIt is important that the design community does not neglect the danger of counterfeit batteries. Imitation or aftermarket batteries have resulted in public relation issues for portable equipment manufacturers because these counterfeits are usually of lower quality than the original battery. While protection of business is a side effect of adding authentication, the main benefit to OEMs comes from the protection of their corporate names and reputations. The intangible qualitative impact negative affect on the device manufacturer's brand name equity cannot be underestimated since safety and performance are both compromised in the production of aftermarket battery packs.
Jeffrey VanZwol is marketing director for Micro Power Electronics.
| Power Efficiency - Latest Trends and Techniques
Efficiency is a key technology driver in all areas of power conversion now. For utility-connected applications, new regulatory initiatives like 85-plus and EnergyStar, combined with a more "green-conscious" consumer are driving power management architectures to new levels of efficiency. The same is true for portable and battery-powered applications, where longer run-times are enabled by more efficient power conversion. One area of improvement is that OEMs are paying closer attention to the power consumption duty-cycle of products, and optimizing converter efficiency over a broad range of multiple load points, not just peak efficiency at one "sweet-spot."
For the common buck converter topology, using control techniques like constant on-time control rather than fixed-frequency PWM can provide an efficiency curve with a much broader range of efficient operation, particularly down to the lower load levels. For applications with RF sections, the frequency-range must often be constrained so that the switching frequency and its harmonics don't potentially interfere with the radio section.
For higher power applications with multi-phase power converters, light-load efficiency can be improved using phase-shedding techniques, where the number of active phases (and their relative phase) is dynamically allocated depending on the load at that moment.
But the major limiting factor to even better efficiency is still the power switch itself. Improving the switch Figure-Of-Merit (FOM) benefits all of these topologies and techniques.
One promising trend is the application of Gallium Nitride (GaN) power devices in power converters, in place of conventional Silicon FETs. Early results indicate that GaN power FETs will offer not only much lower specific on-resistance, but far better (lower) capacitance as well. This combination of improved switch parameters points to more efficient converters operating at today's switching frequency, or higher density converters capable of efficient operation at much higher frequencies. Either way, the pending introduction of GaN power FETs promises improvements in converter performance for wireless applications.
High Power Efficiency Microwave and mm-Wave Power Amplifiers
In both communications and radar systems, phased array antennas are increasingly being favored over conventional mechanically-scanned systems. Applications in military scenarios, using active electronically-scanned arrays (AESA) require an efficient source (or sources) of microwave power. Today and into the foreseeable future, RF semiconductor power amplifiers (mainly MMICs) are used to supply the required power to each individual element in the active array. At Mimix we have successfully used commercially available GaAs foundry technologies to extend the power added efficiency (PAE) of Ku-band and Ka-band power amplifiers used in radar systems by load pull based selection of gate length, gate width and thermal attributes and modeling. Backed by extensive use of EM simulations on graded impedance and harmonically terminated device combiners, these solutions extend the capabilities and bandwidths of existing solutions without sacrificing quality or lifetime in adverse environments.
In the design of any power amplifier, load pull data is a necessary foundation. In our existing load pull, we have also studied the impact of cell layout on the optimal efficiency performance versus frequency, typically limited by the transistors drain-source capacitance, CDS and its on-state resistance, RON or knee voltage. Load pull also helps us identify the optimal fundamental and harmonic terminations. In review, typically drain efficiency increases with larger load impedance but at the expense of power. Therefore, the operating voltage should be set so that the peak voltage swing is equal to the breakdown voltage of the device. This achieves the highest output power for a given load efficiency. Careful selection of the cell combining network approach also has shown it is capable of tuning a fairly wide range of load impedances, while maintaining a high 3rd harmonic impedance and realizable transmission line impedances.
Techniques for Improving Wireless Infrastructure Power Efficiency
The maximum operating frequency of point-of-load DC/DC converters has been trending upward beyond 1 MHz for several years, allowing for smaller output inductors and capacitors. The penalty is increased gate drive and switching losses proportional to the switching frequency that reduces efficiency. Many designers resort to lower operating frequencies around 500 kHz to improve efficiency and address minimum on-time constraints. Improved process and package technologies produced new monolithic and multi-chip modules with integrated MOSFETs with a 25% lower drain to source on-resistance than previous generations. Designers now can take advantage of space savings offered by integrated MOSFETs without sacrificing efficiency. For example, TI's TPS54620 delivers 6 A from a 12 V rail in a small 3.5 x 3.5 mm package, smaller than most performance DC/DC controllers requiring external MOSFETs.
If board space is available, a DC/DC controller with external MOSFETs can improve efficiency with lower resistance MOSFETs. Consider power MOSFETs with a low figure of merit, or the on-resistance multiplied by the gate charge. The power loss gap between a MOSFET with best-in-class gate charge performance and a traditional MOSFET widens with increasing switching frequency. For instance, power MOSFETs with NEXFET Technology can deliver a 2 to 5% efficiency gain due to improved gate charge and on resistance characteristics.
Traditionally, using OR-ing power diodes was a simple method used to combine battery back-up or redundant power supplies to ensure wireless application reliability. Using MOSFETs instead provides higher efficiency since the voltage drop across a MOSFET is much lower than a diode. For example, a 12 V, 5 A application can save up to 5 W by using an OR-ing FET controller versus OR-ing diodes. A 12 V, 20 A application can save as much as 15 W. The TPS2410 is a full-featured OR-ing FET controller that controls power rails from 0.8 to 16.5 V.
Got a Power Problem? Fix it in the Architecture Using ESL
Power consumption is a key consideration in semiconductor design today. Formerly secondary to performance and area, it has become a first-order concern, especially for consumer electronics and other battery-powered devices.
Multiple approaches reduce power in the RTL-to-GDSII flow. Although helpful for power reduction in RTL architectures, they are even more effective on architectures that are power-efficient to begin with. This is why there is tremendous interest in power optimization at the ES Level – before the RTL architecture is selected.
A design’s power consumption is highly dependent on its RTL architecture. Once that architecture has been set, 80 to 90% of the power budget is set in stone. By starting at the ES level, a design team has the opportunity to perform a system-level power analysis to measure switching activity, which drives synthesis and optimization of a low-power RTL architecture using a power-optimizing high-level synthesis tool.
Unlike timing and area, circuit power consumption is significantly impacted by the data moving through it. Therefore, power analysis must rely on a set of real, expected mission-mode vectors to ensure highly accurate implementation of a low-power architecture. This data is best obtained by simulating the entire system, possibly executing software on a system-level hardware model. This is another important reason why power analysis and optimization are addressed most effectively at the ES level.
Benchmark results of this methodology have proven that power consumption can be significantly reduced at the ES level – by as much as 75 to 80% compared to RTL designed by hand, or to non-power-optimizing high-level synthesis. Power approaches at the RT level and below still add significant value, particularly combined with ESL power optimization that passes power constraints forward in a standard format such as UPF.
There are many reasons to adopt ESL. But with the emergence of power-optimizing high-level synthesis, power reduction is becoming one of the most compelling reasons to adopt an ESL approach to design.
Techniques Available for Improving Power Efficiency in Wireless Designs
In the world of DC/DC converter design there are two key areas for consideration when it comes to maximizing power efficiency: conversion efficiency and thermal management. In an ideal situation, the input voltage range would be tailored to be as close to the output voltage as possible in order to achieve optimal efficiency. In reality, system designers are often challenged to develop a system solution that can be implemented globally, where different BUS voltages such as 3.3V, 5V, 9.6V or 12V may be present.
Today, designers can typically choose from modules that have relatively wide input ranges of either 2.4V to 5.5V or 8.4V to 14V, but these only address limited nominal input voltages. In the near future, Murata Power Solutions will begin to offer devices with an even wider input voltage range of 4.5V to 14V, thereby enabling coverage of 5V, 9.6V and 12V nominal input voltages with one DC/DC converter.
Having widened the input voltage range, Murata Power Solutions is still able to minimize conversion losses – and therefore maximize efficiency - by using ‘dead time control’ also sometimes known as ‘adaptive gate drive’. This technique uses precise control circuitry to minimize the delay (to the sub nano-second region) between when the rectifier MOSFET turns off and the main switch turns on and vice-versa – a basic function of most DC/DC converters. By keeping dead time to a minimum, the voltage and current spikes that are contributors to poor efficiency are also minimized. This technique brings an additional benefit: improved EMI performance of the DC/DC converter.
Last but certainly not least is the application of sound thermal management techniques. As form factors continue to shrink, designers face the challenge of dissipating power via increasingly smaller surface areas. Industry leaders such as Murata Power solutions employ novel thermal management techniques to maximize the available surface area for heat transfer. By optimizing the conversion efficiency of the DC/DC and making best use of the available surface area for conduction cooling, improved derating performance at high ambient temperatures can be achieved.
Saving Power with Ambient Light Sensors
Power management has always been a concern in mobile system design. Today, as liquid crystal displays (LCDs) grow larger in size and higher in resolution, the power demands of the displays are ever increasing. Example: In Smartphones, system power consumption is continuing to increase due to the use of ever-demanding software applications. Consequently, the focus has turned to reducing power in other areas of the system. Many designers have turned to ambient light sensor (ALS) technology to achieve further power reduction in the display. As a result, battery life can be significantly extended by lowering the average power consumption of the LCD.
In battery-powered devices, a large high-resolution display may consume as much as 30% of the total system power. As much as 90% of that power may be consumed by the display backlight unit (BLU), which in part controls the display illumination and brightness. The brighter the display, the more power the LCD consumes; dimming the screen will save battery power effectively by reducing the power consumption of the LCD backlight unit. Dimming the screen in lower lux* level environments can also be implemented with minimal to no impact on the viewing quality of the end user. Since the system manages the LCD power consumption relative to ambient light, the lower the average ambient light during use, the lower the power consumption of the display. Proximity detection combined with ALS is an emerging application for mobile devices such as Smartphones with touch screens. Proximity detection offers additional benefits for BLU power management by enabling the display to be turned on or off when the presence or absence of a user is detected.