Ken Karnofsky on Reducing Development Time of Optimized Digital Receivers
In today's podcast we talk to Ken Karnofsky, Senior Strategist for Signal Processing Applications at MathWorks. Ken talks to us today about Semtech Corporation's use of MATLAB and Simulink products to reduce development time of optimized digital receivers in wireless RF devices.Hosted by Janine E. Mooney, No Strings Attached - Your Wireless Broadcast, is Wireless Design and Development's web-based interview show where we talk about the latest wireless technology, components, and design issues for the wireless design engineering community.
Here is another link to the podcast in case the playback button is not working: MathWorks-KenKarnofsky
About Ken Karnofsky
Ken Karnofsky is the Senior Strategist for Signal Processing Applications at MathWorks. Through his 20 years of experience, first with BBN Technologies, then with MathWorks, Ken has been involved in development and marketing of software for signal processing and data analysis technologies. Ken holds a degree in Systems Engineering from the University of Pennsylvania.
Here is a recent press release on MathWork's efforts:
MathWorks announced Semtech Corporation used MATLAB and Simulink products to reduce development time of optimized digital receivers in wireless RF devices. Semtech, a leading supplier of high-quality analog and mixed-signal semiconductors, adopted Model-Based Design tools to create FPGA prototypes 50% faster than before, reduce verification time from weeks to days and shorten development time by 33%.
A Simulink model based on system specifications helped engineers rapidly evaluate design ideas and improved collaboration among engineering teams. Simulink and Simulink HDL Coder enabled engineers to create prototypes in a few weeks and eliminate hand-coding. Using EDA Simulator Link, Semtech engineers reused the Simulink system model to test multiple critical points in the design, verify the VHDL in less than a day, and reduce overall verification time from weeks to days.
"We were tasked with the challenges of accelerating the development time for a digital receiver and finding a way to improve our development workflow. MathWorks tools enabled us to explore more alternatives and new features, and ultimately deliver a more optimized, better performing design," said Frantz Prianon, IC design engineer at Semtech. "With Simulink and Simulink HDL Coder, once we have simulated the model we can generate VHDL directly, prototype on an FPGA, and fully verify the VHDL implementation. It saves a lot of time, and the generated code contains some optimizations we hadn't thought of."
"Semtech represents the leading edge of semiconductor companies that are transitioning to new methodologies for highly integrated mixed-signal devices. With Simulink and Model-Based Design, Semtech was able to evaluate multiple design ideas at the prototyping stage and eliminate bottlenecks in their development workflows," said Ken Karnofsky, senior strategist for signal processing applications, MathWorks. "Further, automatic HDL code generation with Simulink HDL Coder allowed Semtech to eliminate coding errors and quickly create a working FPGA prototype."
Signal Processing Toolbox, DSP System Toolbox, Fixed-Point Toolbox and Simulink Fixed-Point all helped further accelerate the development of the digital receiver. Model-Based Design has enabled Semtech to transition to a fully digital platform, advance digital and mixed-signal designs, and reduce power consumption while supporting design-flow integration with other products such as Mentor Graphics Questa Advanced Simulator. Semtech is currently working on an ASIC implementation of the receiver.
More details on Semtech's use of MathWorks tools can be found in the user story, "Semtech Speeds Development of Digital Receiver FPGAs and ASICs" available at: http://www.mathworks.com/company/user_stories/Semtech-Speeds-Development-of-Digital-Receiver-FPGAs-and-ASICs.html?by=company
Posted by Janine E. Mooney, Editor
November 18, 2011