Low-Noise Timing Chipset for Wireless Base Station Radio Cards

Fri, 06/21/2013 - 10:39am

Integrated Device Technology (IDT) (NASDAQ: IDTI) has announced a low-noise timing chipset optimized for use in wireless base transceiver station (BTS) radio cards. The new chipset complements IDT’s extensive communication signal chain portfolio, offering engineers the tools needed to solve phase noise-related challenges and build cutting-edge wireless systems.

The IDT 8V19N4xx chipset is a flexible JESD204B-compliant radio frequency phase-locked loop (RF PLL) and clock synthesizer, designed to meet both the high frequency and low phase noise requirements for 2G, 3G and 4G LTE wireless infrastructure. Leveraging IDT’s proven FemtoClock NG technology, the low phase noise characteristics enable the system’s analog-to-digital and digital-to-analog converters (ADCs / DACs) to function with high precision and very low distortion levels. This results in improved signal integrity on transmission and enhanced signal sensitivity on reception, increasing data throughput via lower bit error rates (BER). Furthermore, reduced noise in the RF signal path enables base-station developers to decrease cost and complexity by relaxing the system’s filter requirements.

“At IDT, we recognize the undesired effects noise can cause in the RF signal chain, and have developed this timing chipset to provide system engineers a new tool to address it,” said Christian Kermarrec, vice president and general manager of the Timing and Synchronization Division at IDT. “Our new chipset also offers several key features, such as JESD-compliant clocking and integrated clock jitter attenuation for easy integration into our customers' specific architectures. The new timing devices complement our industry-leading timing portfolio as well as our performance-leading data converters, data compression, RapidIO, and RF signal chain products for wireless infrastructure applications.”

The IDT 8V19N4xx chipset generates synchronized and highly configurable clock and SYSREF signals as required by JESD204B applications. This allows customers to use a standard, cost-effective timing chipset with a high degree of flexibility instead of multiple PLLs, synthesizers, and buffers. In addition, the devices feature integrated clock jitter attenuation to simplify system design, and support a low-cost, low-frequency external VCXO to reduce system cost.


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