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16-bit DAC Slashes Power Consumption 65 percent, Increases Speed 25 Percent

Fri, 04/15/2011 - 10:27am
Texas Instruments Incorporated (TI) today introduced the industry’s most power-efficient 4-channel, 16-bit DAC (digital-to-analog converter). At 1.25 GSPS, the DAC3484 is 25 percent faster than the next fastest quad DAC while consuming as little as 250 mW per channel – 65 percent less than the closest competitor. The DAC3484 is also 40 percent smaller than alternative quad DAC solutions while enabling wideband power amplifier linearization of up to 250 MHz. The wider input bus DAC34H84 or the 2-channel DAC3482 are available to support a linearization bandwidth up to 500 MHz. Key features and benefits include: * 16-bit interleaved 1.25-GSPS input halves the I/O count, reducing FPGA costs and simplifying board routing. * 9-mm x 9-mm Multi-row QFN package enables higher-density main and diversity transmitters. * Low-jitter 2x to 32x phase locked loop eliminates the need for an external, low-jitter clock multiplier to match the interpolated rate. * 2x to 16x interpolation and two independent 32-bit NCOs (numerically controlled oscillators) lower the interface rate and cost of FPGAs, while providing flexibility in frequency planning. * Offset, gain, group delay and phase control for system calibration significantly improve sideband suppression for wideband signals when interfacing with IQ modulators, such as the TRF372017, in direct up-conversion radios. Evaluation modules (EVMs) are available now for $499. The DAC3484EVM, DAC3482EVM and DAC34H84EVM include the TRF370315 IQ modulator and CDCE62005 clock jitter cleaner, as well as TI power management devices, such as DC/DC converters and low-noise LDOs, to provide a complete bits-to-RF prototyping and reference design. The EVMs are also compatible with the GC5330SEK, a complete transmit, receive and digital pre-distortion system evaluation kit and reference design for power amplifier linearization. Additionally, the TSW3100 pattern generation module features a high-speed double data rate LVDS (low-voltage differential signaling) data output bus that provides 16 bits of data at 1.25 GSPS per bit. When combined with the DAC3484EVM, the TSW3100 enables easy data pattern generation while offering a flexible evaluation environment. The DAC3484 and DAC3482 are sampling today in a 9-mm x 9-mm Multi-row QFN package. Production quantities will be available in 2Q11 for a suggested retail price of $58.60 for the DAC3484 and $33.50 for the DAC3482 in 1,000 unit quantities. The DAC34H84 is also sampling now in a 12-mm x 12-mm BGA package. Production quantities will be available in 2Q11 for a suggested retail price of $60 in 1,000 unit quantities. For more information and to order samples, visit www.ti.com/dac3484-pr
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