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Moore’s Law Meets RF

Fri, 02/08/2013 - 9:09am
Bill Driver, National Instruments

The development pace and proliferation of mobile devices places new demands on automated test.

The byproducts of Moore’s law have increased the performance and reduced the cost of electronic products across every industry for more than half a century.  The development pace and proliferation of mobile devices today have leveraged Moore’s law, growing at a projected 24.9% CAGR for 2011 – 2017 (ovum.com, May 3, 2012). This trend is fueling significant silicon process developments in consumer electronics and signal processing for features necessary to meet the demand.

From a test and measurement perspective, traditional box instruments have not kept pace with this growth in an affordable or efficient manner. Because of extremely stringent performance requirements, the instrumentation space has often relied on more traditional discrete design methodologies. Despite delivering world-class accuracy and stability through these methods, box instruments are extremely expensive, complicated to design. They fail to leverage the benefits of integration and therefore often fall behind the pace of change inherit in the devices they aim to test.

Users of RF instrumentation will soon benefit greatly from three trends that shift RF instrumentation on a trajectory to match Moore’s law: Advanced CMOS technology, greater FPGA utilization, and reduced form factors.

Advances in CMOS Technology

In traditional RF test equipment design, the signal manipulation has been implemented predominantly in the analog domain. This means that large and complex analog systems need to be developed to amplify, filter, mix, and manipulate electric signals while dealing with the physical realities of nonlinearity, noise, coupling, interference, power dissipation, and so on.

This is complex work that requires significant investment and skill on the part of the instrument developer, leading to expensive instrumentation. 

An alternative approach is to convert the signals to the digital domain with a reduced amount of analog signal processing, resulting in a less expensive and more flexible design.  This requires better data converters with improved bandwidth capability, increased linearity and reduced noise.

Figure 1 shows the distribution of CMOS nodes used for scientific ADCs over time. Color represents the number of publications at each geometry. The scaling trend plotted on early adopter state-of-the-art data points shows an 2x reduction in geometry scaling every 3.75 years. It also shows that there are certain preferred technologies for analog development such as 180 nm in previous years, and now 90 and 45 nm. The shrinking geometries are required to reduce power consumption of the DSP portions of the converters, but it is also driven by the trend towards system-on-a-chip (SOC) integration where the analog and digital portions are on the same chip.

Analog Devices states in its 2011 Trends in Data Conversion, “The wireless communications market will remain another key driver of data converter performance, power efficiency, and calculated integration…and it’s clear that the future of high-speed converters in this market will be defined by lower power consumption combined with faster sampling rates and more usable bandwidth at higher intermediate frequencies.” 

Some recent high-performance RF instrumentation incorporates the latest communications infrastructure data converters and zero IF modulators and demodulators. These architectures features several advantages for test equipment users over the traditional architectures including lower cost, less power consumption, and high selectivity. This capability is useful in testing the latest wireless and cellular connectivity standards such as 802.11ac and LTE.

Greater Use of FPGAs in Instrumentation

FPGAs are used extensively for data manipulation and data processing but also for digital signal processing (DSP). DSP is a bit different in the sense that analog signals are converted from the analog into the digital domain by data converters, and then further manipulated in the digital domain.

Having powerful, FPGA-based digital signal processors at the center of test equipment has several advantages. Firstly, FPGAs are parallel in nature and can therefore perform complex mathematical calculations simultaneously without involving a host processor. The digital signal processor can be used to convert large records of data into manageable blocks of information that can then be further processed or stored on the network. Another key advantage of DSP performed on FPGA-based test equipment is that it is reprogrammable, which means that one piece of hardware can be used for various test applications, be it current or future standards-based testing. A software-designed instrument also offers the user the ability to develop a custom application or update the device to the latest test applications. It then truly becomes software-designed test benefitting from the rapid advances of FPGA development that is outstripping that of processors.

EEJournal states that FPGAs have walloped digital signal processors, conventional processors, and even graphics processors - both in terms of raw processing throughput on a single device, and particularly when considering the amount of power consumed.

The power of FPGAs has led to the reduced cost and size of RF test equipment while still providing performance that matches the needs of high-volume RF test. An additional key benefit of using FPGAs is the massive reduction in test time.  Qualcomm Atheros decreased test times by more than 200x over the original solution that used traditional instrument by synchronizing the timing of digital control with the onboard FPGA on NI’s vector signal transceiver with the RF front end of the instrument.

Optimized Form Factor - PXI

Building automated test systems to verify the performance and quality of the latest electronic devices requires a combination of high-performance instrumentation, data buses, processing, and data storage solutions in a compact and reliable form factor. National Instruments introduced PXI in 1997 to meet these requirements and evolve with the advancements of Moore’s Law. For example, the first PXI systems sold in 1998 offered a Pentium MMX 233 MHz processor with up to 128 MB RAM; today’s PXI systems feature a quad-core Intel Core i7-3610QE 2.3 GHz processor with up to 16 GB RAM. This represents a more than 134X improvement in GFLOPS processing performance in the same form factor.

The aforementioned growth in the mobile market implies a rapid adoption of new wireless standards, such as IEEE 802.11 ac and LTE. To meet the ever growing and changing testing demands, test equipment vendors have been designing RF test solutions in the preferred form factor of PXI. Recent PXI products announcements include vector network analyzers, vector signal analyzers, and vector signal generators from vendors such as Aeroflex, Agilent, and National Instruments. Because the PXI form factor is constrained in power (~30W per slot) and size (Eurocard formats), it is forced to adopt the latest technologies in data converters and FPGAs as outlined earlier to remain competitive. Thus, it represents a viable commercial vehicle to ensure delivery of these benefits to RF engineers.

Moore’s Law Beyond 2013

Intel expects computing performance advancements in accordance with Moore’s Law to continue beyond the next 10 years. Not only is this trend fueling significant CMOS and FPGA process developments for consumer electronics, it is fueling advances in the next generation of RF test equipment. We are likely to see additional uses for the technology propelled by fast growing consumer electronic devices which can have a disruptive effect on the cost, footprint, and test throughput of next-generation RF test solutions. 

This is just one of the trends defined in the Automated Test Outlook 2013, which is a report that shares findings of research conducted by National Instruments into the latest test and measurement technologies and methodologies affecting numerous industries.

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