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e-MMC Based Embedded Memory Architectures in Mobile Phones

Wed, 10/20/2010 - 12:55pm
Scott Beekman, Toshiba America Electronic Components, Inc.

The growth of features available in mobile phones has both driven and been enabled by changes in NAND based memory architectures. As phone capabilities evolved, feature rich phones migrated from NOR-based solutions to NAND-based solutions. Today, with the growth of GB1 (Gigabyte) class phones, a variety of NAND-based architecture solutions are available with various tradeoffs to consider.

e-MMC based Embedded Memory
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Figure 1. Embedded NAND Memory Growth within Smartphones.
The increase in demand for Smartphones, for example, and the average storage density supported, highlights the importance of these GB class memory architectures. As shown in figure 1, Forward Insights forecasts that the average embedded NAND capacity used in Smartphones will increase from 7.6GB in 2010 to 50.8GB in 2014. In addition, most phones today support a microSD card slot for added storage.

High Density NAND based Embedded Memory Architectures
Prior to GB class phones, embedded NAND based memory architectures generally incorporated Low Power (LP) SDRAM die and Single Level Cell (SLC) NAND die packaged together in a multi-chip-package (MCP), or alternatively in a package-on-package (POP) which is then stacked on a processor to save board space. DRAM densities typically ranged from 256 Mbit to 2 Gbit and SLC NAND from 512 Mbit to 4 Gbit.

As phones started demanding Gigabytes of storage for music, images, video and applications, the demand for high-density, cost effective Multi Level Cell (MLC) NAND solutions grew. The most popular embedded high-density mobile storage solution is the JEDEC standard e-MMC, derived from the MultiMediaCard standard. e-MMC incorporates one or many MLC NAND die stacked together with a controller that has an MMC interface and manages the error-code correction (ECC), wear leveling and bad block management requirements of the MLC NAND die, relieving the host processor of this task. e-MMC currently supports densities from 2GB to 64GB in package sizes generally ranging from 12mm x 16mm to 14mm x 18mm, although smaller and larger package sizes are also supported.

Today, GB class mobile memory architectures typically fall into two categories as reflected in Figure 2.

e-MMC based Embedded Memory
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Figure 2. Traditional LP SDRAM + SLC NAND with e-MMC added for storage.
In each of these cases, LP SDRAM is used for working memory, SLC NAND for code storage demanding high performance and reliability, and high-density cost-effective e-MMC for data storage.

In case (2), e-MMC is incorporated within the MCP/POP along with LP SDRAM and SLC NAND. The benefit of this is to save board space. When combined as one MCP chip, this solution has only one footprint, or in the case of POP, takes no additional board space when stacked on a processor if the processor can support POP.

Limitations with case (2) are that the maximum e-MMC storage density supported may be limited. For example, in the case of POP where memory package heights are constrained, and therefore the number of memory die that can be stacked are limited, only 4 or 8GB of e-MMC may be supported.

In case (1), greater flexibility may be realized to support a variety of e-MMC storage densities more easily, although this solution adds an additional footprint relative to case (2). e-MMC has relativity few flavors by density, each supporting a common 169ball JEDEC standard footprint. In comparison, the variety of combinations of LP SDRAM + SLC NAND MCP/POP can be many based upon different DRAM and NAND densities, organizations, interfaces such as DDR vs SDR, or other specifications. As a result, by keeping e-MMC as a separate chip, it is much easier to migrate from one density to another, to offer multiple product SKUs, or to make last minute development adjustments in densities based upon changing market needs. It may also lead to a lower priced solution as each chip can be negotiated separately with suppliers optimally suited to support each solution. And potentially lower inventory risk may be achieved as the e-MMC portion of the overall memory is less customized than if it were combined with LP SDRAM and SLC NAND.

New High Density NAND based Embedded Memory Architectures
With the introduction this year of a new JEDEC standard for e-MMC, version 4.4, new memory architectures can be implemented more easily to reduce cost and potentially reduce package height or board space. The new standard supports new security features including increased write protection management, a new secure-access controlled memory block, plus Secure Erase and Secure Trim functions for data erase operations. These features help protect code and OS from malicious access and enable complete removal of data from physical memory so that sensitive personal information for example can be securely erased as desired.

In addition, the new e-MMC version 4.4 standard allows for the NAND memory to be divided into more partitions, as programmed by the host controller (one time programmable). As we see in the example of figure 3, the NAND manufacturer may enable some partitions to be SLC, MLC, or can be programmed as either SLC or MLC by the host controller.

e-MMC based Embedded Memory
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Figure 3. Multi Partitioning Feature in e-MMC Version 4.4.
Those areas requiring better reliability are SLC or can be programmed as SLC. The Boot Area, which stores the boot code, and the Enhanced User Data Area, which may store, for example, system log files, are SLC. The User Data Area, which may store music, pictures, videos and other files is MLC. There are four general-purpose areas that can be configured as SLC or MLC as the handset manufacture desires, with no limit to the proportion that can be configured as SLC up to almost the full density of the e-MMC. Each 1 bit configured as SLC results in 2 bits less of MLC. Theoretically an 8GB e-MMC device (densities are defined in MLC terms), could be configured virtually all as SLC and thus would be approximately 4GB. In most cases, it is more likely that the majority of the memory would be configured as MLC to support higher density.

The benefit of these developments for embedded memory architectures is that the SLC NAND die can be removed, leaving just the LP SDRAM and e-MMC. Thus, new GB class mobile memory architectures can be developed as shown in Figure 4.

e-MMC based Embedded Memory
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Figure 4. SLC NAND removed as Ver4.4 e-MMC supports SLC partitions.
The tradeoffs between (1) and (2) are similar to those mentioned previously. The removal of the SLC NAND die provides additional advantages in addition to reduced cost. In case (1), LP SDRAM can now be supported as a single package as a discrete device or stacked on a processor as POP. Being less customized results in lower inventory risk, and enables more options for sourcing. For case (2), even when LP SDRAM is combined with e-MMC, this is still a less customized solution than if SLC NAND were included.

When determining how much board space to layout for the memory package containing the e-MMC, there is a tradeoff that needs to be considered between cost and board space. From a cost perspective, it is generally better to have less stacks of larger density NAND dies, than more stacks of smaller density NAND dies. For example, 16 GB of e-MMC supported by stacking four 32 Gbit dies would be less expensive than stacking eight 16 Gbit dies. But since a larger NAND die requires more space, the minimum package size that can support 32 Gbit die is larger than that supporting 16 Gbit die.

Today, the high volume, cost effective MLC NAND die density is 32 Gbits. Thus, densities from 4GB to 64 GB are most cost effectively supported by stacking from 1 to 16 die of 32 Gbit MLC NAND. Since these are stacked in a staircase fashion so that the leads can be connected to each die, as opposed to simply placing one die on top of another, it means the minimum package size supporting 64 GB e-MMC would be larger than that of a 4GB e-MMC. The fact that so many e-MMC densities can be supported by the same 32 Gbit MLC NAND die has important implications for lower density e-MMC such as 1 GB or 2 GB. Lower density e-MMC will utilize MLC NAND die which is not the mainstream density (8Gbit or 16Gbit), and therefore suffers from lower supply volumes and economies of scale relative to the 32Gbit MLC die used in 4GB and larger e-MMC.

Conclusion
With the introduction of e-MMC version 4.4, SLC NAND die can be removed enabling lower cost, and potentially reducing package height or board space. Tradeoffs need to be considered between board space and supply flexibility, and therefore potentially overall supply and inventory costs, when determining whether to combine LP SDRAM and ver4.4 e-MMC in one package or to keep separate.

Scott Beekman is a senior business development manager at Toshiba America Electronic Components, Inc.

1When used herein in relation to memory density, gigabyte and/or GB means 1,024x1,024x1,024 = 1,073,741,824 bytes. Usable capacity may be less. For details, please refer to applicable product specifications.

Information in this article including product details and specifications, content of services and contact information is current and believed to accurate as of the data of publication, but is subject to change without prior notice.

Technical and application information contained here is subject to the most recent applicable Toshiba product specifications. In developing designs, please ensure that Toshiba products are used within specified operating ranges as set forth in the most recent Toshiba product specifications and the information set forth in Toshiba’s “Handling Guide for Semiconductor Devices,” or “Toshiba Semiconductor Reliability Handbook.” This information is available at www.chips.toshiba.com, or from your TAEC representative.

              

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