Noise Elimination Power Converter Control Circuit
Wed, 02/25/2009 - 10:46am
Grounding and care in layout is the key to keeping noise out of the control circuit and allowing correct operation. Grounding and care in layout is the key to keeping noise out of the control circuit and allowing correct operation.
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Figure 1. Power converter with ground planes
The down side of these faster switching edges is that high frequency (HF) noise is generated in the process. This unwanted noise can degrade the control signal, resulting in an overall system malfunction. Careful layout and attention to grounding can eliminate most of the noise problems by keeping the signal-to-noise ratio (SNR) high.
Noise Sources and SolutionsTraces that provide voltage feedback and current sensing information are susceptible to injected noise. If they run beside other traces carrying high di/dt currents or dv/dt voltages, noise can be coupled into these traces to drown out the signal. Separating the source and signal trace is necessary.
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Figure 2. Placement of low-pass-filter components
For high dv/dt traces, coupling between the noise source and signal is a function of the capacitance between the two traces. When the signal line crosses the traces with high dv/dt, it should be at 90 degrees to minimize the effective capacitance between the two traces.
Grounding and DecouplingAnother method for reducing interference from noise sources is to use low impedance terminations. A big source of noise is current in the ground plane. Currents from drivers to FET gates can have edges switching at a di/dt greater than 100 A/µs, and dv/dt greater than 200 V/µs. For example, the TPS2817 switching a 1 nF load has a dv of 11.2 V in a maximum of 25 ns, a dv/dt of 450 V/µs.
A ground bounce is the momentary localized variation in the ground plane voltage caused by a current transient. It is either resistively or inductively generated from the FET source to the bulk storage capacitor across the power components.
To turn on a FET switch, these currents originate at the IC's input capacitor, then travel through the drive transistor to the FET's gate. However, they don't stop there. The charge they inject into the FET's gate must complete the circuit. So a return current out of the FET source goes through the ground track back to the IC's input capacitor. This can cause ground bounce because the inductance between the control IC's ground and the FET's source interacts with the high di/dt of the drive current.
When the FET is turned on, the FET's source momentarily will be at a higher voltage than the nominal ground of the IC. When the FET is turned off, the IC's drive pin is shorted to the IC's input capacitor negative terminal. This causes the FET's gate to be discharged through the IC's internal switch. The FET's gate to source capacitor pulls current in from the IC's ground connection. The result is a very high di/dt and a ground transient at the IC's ground pin.
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Figure 3. Appropriate ground planes for a UCC3803 showing power (Vcc) and Vref capacitor placements.
To minimize these currents inside the IC itself, provide two grounds to the IC: the power and the quiet or signal ground. The power ground is connected to VCC (or Vdd depending on the IC nomenclature) through a large high frequency ceramic capacitor. This provides current needed by the switch gate drives and internal drives within the IC.
In the board layout, connect the ceramic capacitor across the VCC and power ground (usually called PGND in a two ground system) as close to the IC as possible. This should be a very tight loop to minimize coupling and reduce the effects of loop inductance. The traces to the FET (or driver) should be above the ground plane that connects back to the PGND pin. This helps minimize the bounce or dip by minimizing the inductance. For a single-layer board, sandwich the drive between the input power (VCC) and the output power ground (PGND).
Theory of Relativity for Power ConvertersIn an IC with two ground pins, the quiet ground (often called ground or designated GND) should have only one connection to the PGND. This is right under the IC. Reference all control signals to this ground. Connect the Vref directly to this ground by a high-frequency, by-pass capacitor in the order of 0.1 µF, or as specified in the controller's data sheet. Place this capacitor directly across the Vref pin to the quiet ground with short traces. Vref is the internal voltage rail within the IC. Therefore, all comparators, operational amplifiers and logic gates derive their power from this source.
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Figure 4a. Conceptual example of parasitic components on the pins of the ICs.
Be sure to isolate this island from external noise sources and do not let the drive traces go over this ground plane. The current and voltages that are part of the power conversion should not be close enough to impart any noise to this ground plane. The circuit, however, cannot work in total isolation.
The circuit is responding to signals being generated in the world outside the control IC. These signals come in from areas polluted with noise, so you may need to filter the incoming signals by a low-pass-filter between the signal source and the IC. Figure 1 shows the power converter's primary side basic elements with ideal grounding.
In Figure 1, it is assumed that drivers are associated with this converter. These share the same ground plane as the power side of the control IC, but they are physically between the IC and the power components. This placement makes certain that the drive signal from the control IC is referenced to the drivers ground. Also, note that the point where the PGND ground (red) connects to the input power return trace (yellow) is close to the bulk capacitor for the switching elements. Ideally, the bulk input capacitor, power FET sources and connection to the PGND plane is a star connection ground point.
Place the bulk capacitor as close as possible to the switching components so that the transient voltages and currents that are part of the power switching cycle are contained in the minimum space. This limits noise injected into the control circuit. If the SNR is not kept high, problems can develop.
Since noise usually occurs at high frequencies, add an RC low-pass-filter to the signal lines as shown in Figure 2. Note that the resistor is placed across the break, between the noisy or power ground where the signal and noise originate, and the quiet or signal ground. This minimizes any noise coupled from the noisy trace to the quiet ground.
The filter roll off frequency should be approximately an order of magnitude higher than the control signal's highest expected frequency. If the 0 dB crossover of the voltage control loop is 10 kHz, choose the filter components on the voltage feedback signal so that the filter 3 dB roll off frequency is at 100 kHz or higher.
ICs with only One Ground PinIf the IC has only one ground, you can still make a two-ground system. The only difference is that the two grounds now terminate at the control IC's ground pin.
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Figure 4b. Conceptual example of parasitic components on the pins of the ICs.
Another problem that can result in a PWM control IC is extreme voltage excursions beyond the design limits of the IC. These can result in internal parasitic devices turning on and latching the IC into a condition that can damage or destroy the control IC as well as the supply it is trying to control. The Laws of Physics apply to all!
ConclusionNoise is relative. If the signals into the IC are kept within the design limits, and the circuit noise is eliminated, the IC should perform properly. If the signals have high levels of noise, the IC cannot determine what the correct action is and will not be able to provide the desired control function. Grounding and care in layout is the key to keeping noise out of the control circuit and allowing correct operation.
John Bottrill is a senior applications engineer at Texas Instruments. He can be reached at firstname.lastname@example.org.